Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1985-03-06

1987-09-15

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Precharge

365210, 307441, G11C 1300

Patent

active

046944320

ABSTRACT:
A semiconductor memory device comprises a plurality of row decoder circuits connected with word lines for selecting memory cells. The row decoder circuits include normal row decoder circuits and spare row decoder circuits which can be selected in place of a normal row decoder circuit in case where a fault occurs in a memory cell selected by a word line connected to the normal row decoder circuit. An RAS signal (precharge signal) is applied to an output line (12) of a normal row decoder circuit through a precharge bus (31). A link element (11p) is inserted in the precharge bus (31). The link element (11p) is an element which can be melted by a laser beam, whereby the normal row decoder circuit associated is maintained in a non-selective state. A clamp circuit (14) is also connected to the output line (12). The clamp circuit (14) is a circuit for maintaining the output line (12) at a prescribed low level when the link element (11p) is melted and the associated decoder circuit is brought into a non-selective state.

REFERENCES:
"Laser Programmable Redundancy and Yield Improvement in a 64K DRAM", Robert T. Smith et al, IEEE Journal of Solid-State Circuits, vol. SC-16, No. 5, Oct. 1981.
"A Low-Power Sub 100 ns 256K Bit Dynamic RAM", Syuso Fujii et al, IEEE Journal of Solid-State Circuits, vol. SC-18, No. 5, Oct. 1983.
"A 256K Dynamic RAM with Page-Nibble Mode", Kazuyasu Fujishima et al, IEEE Journal of Solid-State Circuits, vol. SC-18, No. 5, Oct. 1983.

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