Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1980-03-31

1982-12-28

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365185, 365181, G11C 700, G11C 1140

Patent

active

043665560

ABSTRACT:
A memory cell formed of two serially connected MOS transistors one of which has a floating gate is connected to a series combination of a Y address MOS transistor, a readout selection MOS transistor and an MOS transistor disposed in an output buffer circuit across two DC sources. A writing selection MOS transistor is connected across the series combination of the last-mentioned two transistors. The Y address MOS transistor, the readout selection MOS transistor, the output buffer MOS transistor and the writing selection MOS transistor are all operated in the triode region with V.sub.G -V.sub.TH >V.sub.D and at least one of these MOS transistors has a channel conductivity type different from the channel conductivity type of the memory cell MOS transistors.

REFERENCES:
patent: 3836894 (1974-09-01), Cricchi
patent: 4114055 (1978-09-01), Hollingsworth
patent: 4122547 (1978-10-01), Schroeder et al.
Schroeder et al., "A 1024-Bit, Fused-Link CMOS PROM", 1977 IEEE Internat. Solid-State Circuits Conf., ISSCC Dig. of Tech. Papers, pp. 190-191.
Fukunaga et al., "FA-CMOS Process for Low Power PROM with Low Avalanche-Injection Voltage", IEDM Digest of Tech. Papers (1977), pp. 291-293.

Affiliated with

Also associated with

Rating

Semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1340850