Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Precharge

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Details

36518905, 365194, 365202, 365205, G11C 700

Patent

active

055555233

ABSTRACT:
A semiconductor memory device comprises a plurality of memory cells including at least a first memory cell and a second memory cell, a first bit line connected to the first memory cell, a second bit line connected to the second memory cell and paired with the first bit line, an equalizer connected between the first and second bit lines, an amplifier connected between the first and second bit lines, a first driving signal line connected to the amplifier and drives the amplifier, a second driving signal line connected to the amplifier and paired with the first driving signal line, a driver for driving the amplifier and connected to the first and second driving signal lines and containing a precharger for presetting the potentials of the first and second driving signal lines to a predetermined precharge potential and a driving signal supply circuit for supplying a driving signal to the first and second driving signal lines, and a control circuit for controlling the equalizer and the driver, wherein the control circuit controls the equalizer and the precharger independently so that the precharger continues supplying the precharge potential to the first and second driving signal lines until essentially immediately before the driving signal supply circuit supplies the driving signal to the first and second driving signal lines.

REFERENCES:
patent: 4813021 (1989-03-01), Kai et al.
patent: 5444662 (1995-08-01), Tanaka et al.
patent: 5479374 (1995-12-01), Kobayashi et al.

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