Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1984-01-04

1986-04-29

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365193, G11C 1300

Patent

active

045861676

ABSTRACT:
Disclosed is a semiconductor memory device which is operable in a selected one of page mode and nibble mode, depending upon the length of time in which an external column address strobe signal stays at a specific level. The semiconductor memory device comprises a circuit for discriminating the length of time where the external column address strobe signal is at a specific level with a predetermined period of time. Data is outputted in page mode in response to one of results of such discrimination and in nibble mode in response to the other result of the discrimination. The discriminating circuit may comprise a second internal column address strobe signal generator and a delay circuit. The second internal column address strobe signal generator includes a NAND circuit at its first stage, and the delay circuit is designed to have different delay times at the building-up and downward edges of an input signal applied thereto. The output of the discriminator is used to operate and reset an output circuit whereby one of the output modes is selected.

REFERENCES:
patent: 4156938 (1979-05-01), Proebsting et al.
patent: 4344156 (1982-08-01), Eaton, Jr. et al.
patent: 4491910 (1985-01-01), Caudel et al.
patent: 4510602 (1985-04-01), Engdahl et al.

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