Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1991-06-20

1994-02-15

Mullins, James B.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518909, 365226, G11C 700

Patent

active

052873064

ABSTRACT:
A semiconductor memory device includes a first power source having a non-ground potential V.sub.cc1 terminal and a ground potential V.sub.ss1 terminal. The internal circuit is supplied with power from the first power source. The first power source is dedicated to the internal circuit. The internal circuit selects a memory cell of a memory cell array in accordance with an inputted address. The internal circuit has a first output terminal and a second output terminal the first output terminal outputs one of a pair of potential V.sub.cc1 and V.sub.ss1 and the second output terminal outputs the other of the pair in accordance with the data in the selected memory cell. A second power source has a non-ground potential V.sub.cc2 terminal and a ground potential V.sub.ss2 terminal. The output circuit is supplied with power from the second power source which is dedicated to the output circuit. The output circuit has first and second transistors serially connected between the V.sub.cc2 terminal and V.sub.ss2. The control terminals of the first and second transistors are connected to the first and second output terminals. A third transistor is connected between an interconnection between the first and second transistors connected to a data output from which data is externally outputted and the first output terminal, and the control terminal of the third transistor being connected to the second output terminal.

REFERENCES:
patent: 4661928 (1987-04-01), Yasuoka
patent: 5073872 (1991-12-01), Masuda et al.
patent: 5136542 (1992-08-01), Abe et al.
Wada et al., "A 34-ns 1-Mbit CMOS SRAM", IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987, New York, U.S. pp. 727-732.

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