Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1994-02-24

1995-05-02

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Precharge

365205, 365208, G11C 700

Patent

active

054126053

ABSTRACT:
A sense amplifier including a pair of NMOS transistors connected in series between a pair of bit lines differential-amplifies the potential difference between the pair of bit lines by reducing the source potentials of the NMOS transistors to ground potential. An NMOS transistor is activated for a predetermined time after initiation of a differential amplification by the sense amplifier, whereby the source potentials of the NMOS transistors are controlled so as to attain a potential lower than the ground potential during that predetermined time. As a result, the operation margin of the NMOS transistors is increased during the predetermined time period.

REFERENCES:
patent: 5020031 (1991-05-01), Miyatake
patent: 5313426 (1994-05-01), Sakuma et al.
patent: 5325335 (1994-06-01), Ang et al.
A Circuit Technology for Sub-10-NS ECL 4-MB BICMOS DRAM'S, Takayuki Kawahara et al., IEEE Journal of Solid-State Circuits, vol. 26, No. 11, Nov. 1991, pp. 1530-1537.
Design of Overdrive Sense Amplifier for High-Speed DRAM, T. Tachibana et al., Nov. 1991, IEEE J. Solid-State Circuits, pp. 5-153.
A Tunable CMOS-DRAM Voltage Limiter with Stabilized Feedback Amplifier, M. Horiguchi et al., pp. 75-76, 1990.

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