Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

Patent

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Details

365230, 365200, G11C 1140

Patent

active

044803214

ABSTRACT:
A semiconductor memory device, such as a metal-insulator semiconductor random access memory device, in which erroneous write in which may occur when an input address signal is switched, is prevented. The semiconductor memory device comprises an input/output circuit, having an input circuit portion which receives input data and supplies the input data to a pair of data buses and an output circuit portion which amplifies signals from the pair of data buses and outputs therefrom, and a circuit for detecting a change in input address signal and generating a pulse having a predetermined pulse width when the input address signal changes. The input circuit portion of the input/output circuit operates so as to inhibit the writing in of data during generation of the pulse even if the write-enable signal is supplied to the memory device and operates in accordance with the write-enable signal when the pulse is not generated.

REFERENCES:
patent: 4445203 (1984-04-01), Iwahashi

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