Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1994-11-17

1995-10-03

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

G11C 1300

Patent

active

054557950

ABSTRACT:
A semiconductor memory device comprises a page access mode, a plurality of sense amplifiers for detecting data read from a plurality of memory cells selected based on first address inputs A2 to An, a plurality of latch circuits for latching data from the plurality of sense amplifiers, a reading circuit for reading latch data based on second address inputs A0 and A1 corresponding to the plurality of latch circuits, and a control circuit for controlling the sense amplifier to be activated when only the first address input or both first and second address inputs are changed, and to be inactivated when only the second address input is changed.

REFERENCES:
patent: 5383155 (1995-01-01), Ta
Shigeyoshi Watanabe, et al., "An Experimental 16mb CMOS DRAM Chip with a 100 MHz Serial Read/Write Mode" 1988 IEEE International Solid-State Circuits Conference.

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