Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

Patent

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Details

36523008, G11C 800

Patent

active

050738739

ABSTRACT:
This invention is directed to a device to decode a row address by a row decoder thereafter to latch the decoded signal by a latch circuit, thus allowing the latched signal to drive a memory cell in a memory cell array. Since respective addresses are latched after decoded as stated above, no decode time is included in one cycle time and the cycle time is therefore shortened.

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