Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Testing

Reexamination Certificate

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C365S203000

Reexamination Certificate

active

08045409

ABSTRACT:
A semiconductor memory device includes a plurality of memory cells that are arranged at intersections of a word line with bit line pairs, a precharge circuit that is arranged for each of the bit line pairs and is configured to precharge each of the bit line pairs, and a Y-switch circuit that is arranged for each of the bit line pairs and is configured to select each of the bit line pairs. The semiconductor memory device further includes a mode switching unit that switches the normal mode and the test mode in accordance with a mode selection signal that is externally supplied, a plurality of individual control units that control operation of each of the precharge circuits in accordance with operation of each of the Y-switch circuits in the normal mode, and a block control unit that collectively turns off all of the precharge circuits in the test mode.

REFERENCES:
patent: 5255230 (1993-10-01), Chan et al.
patent: 5956279 (1999-09-01), Mo et al.
patent: 6501692 (2002-12-01), Melanson et al.
patent: 2010/0054062 (2010-03-01), Kobatake
patent: 2000-067598 (2000-03-01), None
patent: 2002-184198 (2002-06-01), None
patent: 2002-313083 (2002-10-01), None

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