Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

Reexamination Certificate

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Details

C365S189150, C365S189160, C365S189170, C365S189190

Reexamination Certificate

active

07486571

ABSTRACT:
Disclosed herein is a semiconductor memory device including, a memory array with memory cells array-like arranged, a read bit line connected to a data output node of the memory cells and shared by a plurality of the memory cells arranged in one direction in the memory array, a write bit line connected to a data input node of the memory cells and shared by a plurality of the memory cells, a sense amplifier for sensing a voltage of the reading bit line, a first sense line and a second sense line connected to the sense amplifier, a read bit line switch for controlling electrical connection and disconnection between the first sense line and the read bit line, a write buffer connected between the second sense line and the write bit line, capable of controlling electrical connection and disconnection between the second sense line and the write bit line.

REFERENCES:
patent: 5317537 (1994-05-01), Shinagawa et al.
patent: 5619456 (1997-04-01), McClure
patent: 7075842 (2006-07-01), Tzartzanis et al.
patent: 2001-291389 (2001-10-01), None

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