Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing

Reexamination Certificate

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Details

C365S203000, C365S104000, C365S196000

Reexamination Certificate

active

07408826

ABSTRACT:
A semiconductor memory device that includes a memory cell array having a plurality of memory cells that are connected between a bit line pair, which transfers data to the bit line pair, a precharge circuit for precharging the bit line pair to a precharge voltage level during a precharge period, and one or more bit line sense amplifiers which are connected between the bit line pair and detect a voltage difference of the bit line pair to amplify a level of the bit line pair. The semiconductor memory device includes one or more FINFETs.

REFERENCES:
patent: 6009024 (1999-12-01), Hirata et al.
patent: 6385159 (2002-05-01), Hidaka et al.
patent: 2003/0193824 (2003-10-01), Tsukikawa et al.
patent: 2005/0017240 (2005-01-01), Fazan
patent: 2006/0227595 (2006-10-01), Chuang et al.
patent: 2006/0270159 (2006-11-01), Weis
patent: 10-2000-0044652 (2000-07-01), None
patent: 10-2005-0027781 (2005-03-01), None

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