Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2007-03-15

2008-09-02

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S189040, C365S230060

Reexamination Certificate

active

07420855

ABSTRACT:
Reducing power consumption of a semiconductor memory device having a serial interface is disclosed. After parallel read-out data from a memory-cell matrix14are held in a data latch17, the parallel read-out data are selected sequentially by a serial output selector18according to timing signals SL0-SL15from a controller20and are outputted serially from an output buffer19as an output data DO. In an activating control unit23, outputting an operation control signal AC to a gate-voltage generating unit21, a drain-voltage generating unit22, and a sense amplifier16is being halted during from when a timing signal SL0is finished to when a timing SL10is finished. Consequently, during the above mentioned period, the unnecessary operations of the gate-voltage generating unit21, the drain-voltage generating unit22, and the sense amplifier16are being halted and then the power consumption thereof can be reduced.

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patent: 6549480 (2003-04-01), Hosogane et al.
patent: 2002/0024230 (2002-02-01), Pfertner et al.
patent: 2007/9253274 (2007-11-01), Miyamoto
patent: 06-259320 (1994-09-01), None

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