Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2006-01-20

2008-09-23

Louis-Jacques, Jacques (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S734000, C714S720000, C714S718000, C714S733000

Reexamination Certificate

active

07428682

ABSTRACT:
In relation to the built-in self-test circuit (BIST circuit) for testing CAM macros, the present invention is intended to provide a means to enable reduction in amount of materials as required for wiring channel region for signal distribution, buffer, FF, etc., and in number of LSI pins, and further, to facilitate mounting on chips. The data generators for CAM testing, inserted between the APG for RAMs and CAM macros, create data to write to the CAM macros by obtaining the address signals directly or by decoding the same signals. The APG is common to all the memory macros, and testing proper to each CAM can be carried out by changing over the operation of the inserted data generators by means of the control signal. The data generators are arranged in the proximity of the CAM macros, the circuits to be tested.

REFERENCES:
patent: 5535164 (1996-07-01), Adams et al.
patent: 6286116 (2001-09-01), Bhavsar
patent: 6550034 (2003-04-01), Riedlinger et al.
patent: 2000-111618 (1998-09-01), None

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