Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Precharge

Reexamination Certificate

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C365S204000, C365S230060, C365S210130

Reexamination Certificate

active

07099214

ABSTRACT:
There is provided a semiconductor memory device capable of performing high-speed reading even when the current capability of memory cells and transistors for charging is decreased, and a bit line capacitance is increased. In a sense amplifier, in addition to a P-type MOS transistor for charging, a P-type MOS transistor and a N-type MOS transistor are provided as a circuit for charging a selected bit line up to a switching level of a determination inverter included in a circuit for determining data of a memory cell, and a bit line is charged at high speed, whereby a read time is shortened.

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patent: 6144600 (2000-11-01), Ogura
patent: 6191979 (2001-02-01), Uekubo
patent: 6487132 (2002-11-01), Bae et al.
patent: 6490199 (2002-12-01), Lee et al.
patent: 6741514 (2004-05-01), Sako
patent: 2-310894 (1990-12-01), None
patent: 4-167298 (1992-06-01), None
patent: 11-328988 (1999-11-01), None
patent: 2000-195286 (2000-07-01), None
Japanese Office Action for Japanese Patent Application No. 2002-368744, mailed May 18, 2006.

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