Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

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365230, G11C 700

Patent

active

046775919

ABSTRACT:
Memory cells are allotted for successive addresses. A row decoder enables not only a row line connected to a memory cell of an address designated by an address signal, but also a row line connected to a memory cell of an address preceding or succeeding the address of the former-recited selected memory cell.

REFERENCES:
patent: 4520465 (1985-05-01), Sood
Pinkham et al., "Video RAM Excels at Fast Graphics", Electronic Design, pp. 161-171, Aug. 18, 1983.

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