Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Precharge

Reexamination Certificate

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C365S204000, C365S230060

Reexamination Certificate

active

06992941

ABSTRACT:
There is provided a semiconductor memory device capable of performing high-speed reading even when the current capability of memory cells and transistors for charging is decreased, and a bit line capacitance is increased. In a sense amplifier, in addition to a P-type MOS transistor for charging, a P-type MOS transistor and a N-type MOS transistor are provided as a circuit for charging a selected bit line up to a switching level of a determination inverter included in a circuit for determining data of a memory cell, and a bit line is charged at high speed, whereby a read time is shortened.

REFERENCES:
patent: 6130846 (2000-10-01), Hori et al.
patent: 6191979 (2001-02-01), Uekubo
patent: 6487132 (2002-11-01), Bae et al.
patent: 6490199 (2002-12-01), Lee et al.

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