Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

Reexamination Certificate

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Details

C365S233100

Reexamination Certificate

active

06928004

ABSTRACT:
A semiconductor memory device for reducing noise influence is disclosed. The device comprises an input circuit for receiving data to be written into a memory cell array and outputting the received data to write buffer circuits that write the received data into the memory cell array; an output circuit for outputting read data to the outside, each of the read data elements having been read out from the memory cell array and amplified by a corresponding sense amplifier; an input controller for controlling the input circuit so that the input circuit receives the received data only during a predetermined period; a plurality of input data lines for transmitting the received data from the input circuit to the write buffer circuits; and a plurality of output data lines for transmitting the data amplified by the sense amplifiers to the output circuit. Each of the input data lines and each of the output data lines are alternatingly and adjoiningly disposed on the semiconductor memory device.

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patent: 5901091 (1999-05-01), Lee
patent: 6151257 (2000-11-01), Jeffrey et al.
patent: 6580653 (2003-06-01), Yamanaka
patent: 6714477 (2004-03-01), Nakayama et al.
patent: 7-211069 (1995-08-01), None
patent: 11-134872 (1999-05-01), None
patent: 2001-167572 (2001-06-01), None

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