Semiconductor memory decoder with nonselected row line hold down

Details Semiconductor memory decoder with nonselected row line hold down Semiconductor memory decoder with nonselected row line hold down

1980-06-02

1982-11-23

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365203, G11C 702

Patent

active

043609023

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention pertains to semiconductor integrated circuits and more particularly to a semiconductor memory in which an unselected row line is held affirmatively to ground to reduce the effect of capacitive coupling from an adjacent selected row lines.


BACKGROUND ART

In a semiconductor memory each of the memory cells is accessed by applying a high voltage level to the row line that drives an access transistor for the addressed memory cells. The row line is activated by a decoder circuit which is driven by a multi-bit memory address signal. The row line selected by the address is driven to a high level by the decoder circuit. Heretofore, it has been a frequent practice to permit unselected row lines to float at times when another row line is selected by the decoder. But as memory circuits have become increasingly dense, there can be greater capacitive coupling between adjacent row lines. When a row line is charged or discharged, a voltage will be capacitively coupled into the adjacent floating row lines and the voltage thus coupled can turn on the access transistors from the memory cells connected to the floating row lines. This inadvertent activation of memory cells can destroy the data states stored therein. The most serious coupling occurs between immediately adjacent row lines. Thus, when these memory cells are later accessed, erroneous data will be read out.
In view of this problem, there exists a need for a circuit to drive the row line selected by the memory address to provide access to the memory cells along that row line, but at the same time to hold the nonselected adjacent row lines affirmatively to ground to prevent charging of a nonselected row line by capacitive coupling.


DISCLOSURE OF THE INVENTION

In a semiconductor memory having an array of row lines, a decoder circuit includes a row driver transistor for each of the row lines in the memory. Circuit means are provided for decoding an address signal for rendering conductive a selected row driver transistors and for rendering conductive the row driver transistor for the adjacent row line on either side of the row line corresponding to the selected row driver transistor. Circuit means are provided for generating a first row line signal for transmission through said selected row transistor to charge the selected row line. Further circuit means are provided for generating a second row line signal for transmission through the row driver transistors for said adjacent row lines to affirmatively hold said adjacent row lines to a low voltage state.


BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following taken into conjunction with the accompanying drawings is which:
FIG. 1 is a schematic illustration of a decoder circuit for activating a selected row line in a semiconductor memory, and holding some unselected row lines, including the adjacent row lines, to ground.
FIG. 2 is a schematic illustration of a circuit generating the RD0 and RD1 signals utilized in the circuit of FIG. 1,
FIG. 3 is a schematic illustration of a circuit for generating a CT0 signal utilized in the circuit of FIG. 1, and
FIG. 4 is a schematic illustration of a circuit for generating the signal CT1 which is utilized in the circuit of FIG. 1.


DETAILED DESCRIPTION

Referring to FIG. 1 there is illustrated a decoder circuit in accordance with the present invention. The circuit 10 includes a decoder OR circuit 12 which comprises a plurality of input transistors 14-22. Each of the input transistors has a drain terminal thereof connected to a power terminal 24 which is in turn connected to the power source V.sub.cc. The source terminals on the input transistors 14-22 are connected to a node 26. Address bits A.sub.1 -A.sub.5 are provided respectively to the gate terminals of transistors 14-22.
A precharge transistor 28 has the drain terminal thereof connected to node 26, the source terminal thereof connected to a common ground node 30 and the gate t

REFERENCES:
patent: 3980899 (1976-09-01), Shimada et al.
patent: 4074148 (1978-02-01), Sato
patent: 4074237 (1978-02-01), Spampinato
patent: 4259731 (1981-03-01), Moench

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