Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-04-19
2001-09-25
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
Reexamination Certificate
active
06295237
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a semiconductor memory configuration addressed via word lines and bit lines and having a memory cell array containing a multiplicity of memory cells and redundant memory cells. The redundant memory cells, in the event of failure of the memory cells of the memory cell array, replace the memory cells as spare memory cells, the memory cells of the memory cell array and the spare memory cells being provided on a semiconductor chip.
Semiconductor memory configurations, such as, for example dynamic random access memories (DRAMs), cannot, in practice, be fabricated without failure of memory cells in the memory cell array. This is primarily due to the impinging of undesirable particles during wafer processing in the course of the fabrication of the semiconductor memory configuration, and also to other reasons, such as short circuits, etc. In order to be able to overcome the problems associated with this, therefore, use is generally made of redundant memory cells with redundant bit lines and word lines which can replace memory cells that have failed in this way.
In practice the procedure is such that after the fabrication of a DRAM, still at the wafer level, a test is performed which is intended to localize all failed memory cells of the DRAM. Such failed memory cells may be individual memory cells, groups of memory cells or even complete bit lines and word lines with the corresponding memory cells. Once the failed memory cells have been identified, which is done via a corresponding addressing, the addresses of the failed memory cells and, if appropriate, groups of memory cells and also word lines and bit lines are stored in an external computer. The external computer then carries out a complicated calculation involving the failed memory cells, on the one hand, and the available spare memory cells, on the other hand. In this case, “memory cells” should, of course, also be understood to be groups of memory cells and also, if appropriate, entire word lines and bit lines with corresponding memory cells. This calculation determines how the failed memory cells can be replaced by the spare memory cells in an optimum manner. The calculation is extremely complex, this being due in no small part to the fact that the highest possible yield is striven for. In other words, the failed memory cells are intended to be replaced by the redundant memory cells in such a way that as few redundant memory cells as possible are required, that is to say that the number of spare memory cells is intended to be kept small.
On account of the complicated calculation, to date no thought has been given to using built-in-self-test (BIST) technologies precisely in the case of DRAMs, even though BIST per se has been used for a relatively long time in microelectronics. This is because with BIST, the necessary calculations for optimum use of the redundant memory cells instead of the failed memory cells cannot be performed without a great deal of area being taken up on the wafer. In other words, these calculations presuppose a BIST computing unit, the area requirement of that by far exceeds the acceptable amount in the context of fabricating DRAMs.
Thus, a problem is presented which at first sight appears to be irresolvable. In the context of assigning the redundant memory cells as spare memory cells to the failed memory cells, the use of an external computer is complicated and should be avoided if possible. Recourse to the inherently widespread BIST technology is not possible, however, since using this technology would result in taking up too much area on the wafer of the semiconductor memory configuration. For this reason, to date no thought has been given to using BIST technology in the context of fabricating DRAMs in order to replace failed memory cells by redundant memory cells.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a semiconductor memory configuration with a built-in-self-test that overcomes the above-mentioned disadvantages of the prior art devices of this general type, which, without a complicated external computer, is none the less able to replace failed memory cells with redundant memory cells.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor memory configuration, including:
a semiconductor chip;
word lines disposed on the semiconductor chip;
bit lines disposed on the semiconductor chip;
a memory cell array disposed on the semiconductor chip and addressed via the word lines and the bit lines, the memory cell array having a multiplicity of memory cells;
redundant memory cells disposed on the semiconductor chip and addressed by the word lines and the bit lines, the redundant memory cells in an event of failed memory cells of the memory cell array replace the failed memory cells as spare memory cells; and
a built-in-self-test computing unit disposed on the semiconductor chip and connected to the memory cell array and the redundant memory cells, the BIST computing unit assigning the spare memory cells to the failed memory cells, the BIST computing unit having a register for storing addresses of the word lines and the bit lines of the failed memory cells, the BIST computing unit having a counter and, for each of the addresses, the counter increments a number relating to the failed memory cells as a hit value up to an upper limit, a corresponding one of the word lines or the bit lines being replaced in an event of the upper limit being exceeded.
The object of the invention is achieved by virtue of the fact that a BIST computing unit is provided in the semiconductor chip, which computing unit assigns spare memory cells to the failed memory cells.
In this case, a particular algorithm is used for this assignment, in which the algorithm, for example, a number of failed memory cells is stored as a hit value for each address. If the hit value reaches a specific limit, then the entire word line (X-direction) or bit line (Y-direction) associated with this address is replaced. Individual defects can otherwise be replaced optionally by a word line or a bit line.
The BIST computing unit has, in particular, a register in which the addresses of the failed memory cells can be stored for the individual word lines and bit lines. The register may, for example, be configured as a stack register and act as an associative memory.
To summarize, therefore, in the case of the memory cell configuration according to the invention, the address information for failed memory cells is not stored in an external memory but rather on the semiconductor chip itself in registers. With the aid of a special algorithm, the number of required registers can be kept small in this case. The BIST computing unit then specifies the redundant memory cells that repair the failed memory cells as spare memory cells.
In this way, the semiconductor memory configuration according to the invention does not require an external computer and succeeds with a manageable number of register entries, which results in that only a small amount of chip area is required for the realization thereof. Since the address information of the failed memory cells is stored in real time, high-speed processing is possible which, in particular, also does not necessitate an interruption during a test pass. Furthermore, it is possible to accumulate information about failed memory cells for a plurality of individual test passes in the registers.
If different failed memory cells are present on the same bit line or word line, then the provision of a counter unit which, for each X-address and Y-address, stores the number of failed memory cells as a hit value up to an upper limit makes it possible to restrict the information to be recorded which would occur when a multiplicity of failed memory cells occurred in the same bit line or word line.
Finally, the configuration of the register as an associative memory also has a favorable effect on attaining a high operating speed.
Other features which are considered as
Greenberg Laurence A.
Infineon - Technologies AG
Le Vu A.
Lerner Herbert L.
Stemer Werner H.
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