Semiconductor memory comprising dual charge storage nodes...

Details Semiconductor memory comprising dual charge storage nodes... Semiconductor memory comprising dual charge storage nodes...

2010-07-20

2011-12-13

Stark, Jarrett (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S242000, C257SE21681

Reexamination Certificate

active

08076712

ABSTRACT:
A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

REFERENCES:
patent: 6716686 (2004-04-01), Buynoski et al.
patent: 7399675 (2008-07-01), Chindalore et al.
patent: 2005/0259475 (2005-11-01), Forbes
patent: 2006/0273404 (2006-12-01), Scheuerlein
patent: 2006130801 (2006-12-01), None

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