Semiconductor memory circuit including bias voltage generator

Details Semiconductor memory circuit including bias voltage generator Semiconductor memory circuit including bias voltage generator

1986-08-15

1989-03-28

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365226, 307297, G11C 700, G11C 1140

Patent

active

048170550

ABSTRACT:
A semiconductor memory circuit includes therein a bias voltage generator which produces a bias voltage to be supplied to a control gate of a field effect transistor (FET) which forms a part of each memory cell in the semiconductor memory circuit. The bias voltage generator is comprised of a bias voltage generating source which is sandwiched by first and second FET's. The second FET operates to stop a driving current flowing through the bias voltage generating source, in a standby mode, and the first FET operates to produce an output voltage near to the bias voltage. The bias voltage is generated by the bias voltage generating source when both the first and second FET's are turned ON, in an active mode, and the driving current flows therethrough.

REFERENCES:
patent: 4068140 (1978-01-01), Lou
patent: 4069430 (1978-01-01), Masuda
patent: 4195356 (1980-03-01), O'Connell et al.
patent: 4368524 (1983-01-01), Nakamura
patent: 4384220 (1983-05-01), Segawa
patent: 4609833 (1986-09-01), Guterman

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