Semiconductor memory circuit including a data output circuit

Details Semiconductor memory circuit including a data output circuit Semiconductor memory circuit including a data output circuit

2001-01-26

2002-01-22

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S233100, C365S205000

Reexamination Certificate

active

06341086

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor circuit including a data output circuit, and particularly to a data output circuit capable of outputting data rapidly.
A synchronous dynamic random access memory (herein after “SDRAM”) operates synchronized with a clock signal supplied from the outside. A frequency of the supplied clock signal of the SDRAM tends to be high since the frequency of the clock signal controls an operation speed of the SDRAM.
Data of the SDRAM are output in synchronous with the clock signal after a certain number of clock pulses are passed after a read command signal is input. The certain number is called as CAS latency (herein after “CL”).
In the SDRAM, the data are amplified by a sense amplifier located near an output circuit. Then, the amplified data are output from the output circuit. When the read command signal is input, the data are transferred to the sense amplifier in response to the clock signal and the transferred data are amplified by the sense amplifier. The amplified data are transferred to the output circuit. The output circuit is controlled by a control signal that is synchronized with the clock signal. The data are finally output in response to the clock signal.
A read out time from a memory cell does not depend on a cycle of the clock signal. Therefore, a data storing circuit capable of corresponding wide range clock cycle which does not relate to a number of CL is required for the purpose of outputting data after CL is passed from the input of the read command.
Further, where the SDRAM operates in synchronous with leading edges and falling edges of the clock signal, the control signals should be synchronized with the leading edges and the falling edges of the clock signal. Therefore, circuit configuration of the control circuit turns complex.
SUMMARY OF THE INVENTION
With the foregoing problems in view, it is an object of the present invention to provide an output circuit which can operate with high speed even though the cycle of the clock signal turns short.
It is another object of the present invention to provide an output circuit which can operate in synchronous with the leading edges and the falling edges of the clock signal.
A semiconductor memory circuit according to the present invention comprises a sense amplifier, a first data storing circuit for temporally storing and outputting the data from the sense amplifier in response to a latch signal and erasing the stored data in response to a first clear signal, a first determination circuit for determining whether the first data storing circuit stores the data and outputting a first determination signal representing the determination. The semiconductor memory circuit further comprises an output data bus, a first transfer circuit transferring the data output from the first data storing circuit to the output data bus in response to the first determination signal, a first clear signal generation circuit for generating the first clear signal in response to the first determination signal, a second data storing circuit for temporally storing and outputting the data output from the first data storing circuit in response to the latch signal and erasing the stored data in response to a second clear signal, a second determination circuit for determining whether the second data storing circuit stores the data and outputting a second determination signal representing the determination, a second transfer circuit for transferring the data output from the second data storing circuit to the data bus in response to the second determination signal and a second clear signal generation circuit for generating the second clear signal in response to the second determination signal.


REFERENCES:
patent: 4849937 (1989-07-01), Yoshimoto
patent: 5311471 (1994-05-01), Matsumoto et al.
patent: 5877990 (1999-03-01), Kim

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