Semiconductor memory circuit having data buses common to a plura

Details Semiconductor memory circuit having data buses common to a plura Semiconductor memory circuit having data buses common to a plura

1996-02-15

1997-06-17

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Simultaneous operations

36518905, 36523006, 36523008, G11C 800

Patent

active

056403518

ABSTRACT:
According to the present invention, a data bus common to a plurality of memory cell arrays is formed by selecting a column so as to prevent a data collision from occurring. Specifically, two memory cell arrays have each of data buses in common. A column decoder is supplied with a control signal to control a column selection logic circuit. The column selection logic circuit is so controlled that the data read out to the data buses in response to the control signal is prevented from colliding with each other during the simultaneous access to the two cell arrays.

REFERENCES:
patent: 5392242 (1995-02-01), Koike
patent: 5428573 (1995-06-01), Watanabe
patent: 5499218 (1996-03-01), Ahn et al.

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