Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-09-10
2004-12-07
Nguyen, Van Thu (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S245000, C438S239000, C438S388000
Reexamination Certificate
active
06828192
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present patent application relates to a semiconductor memory cell and a method for fabricating it. The semiconductor memory cell contains a selection transistor and a trench capacitor formed in a trench.
Memory devices, such as dynamic random access memories (DRAMs), for example, contain a cell array and an addressing periphery, individual memory cells being disposed in the cell array.
A DRAM chip contains a matrix of memory cells that are disposed in the form of rows and columns and are addressed by word lines and bit lines. Data are read from the memory cells or data are written to the memory cells by the activation of suitable word lines and bit lines.
A DRAM memory cell usually contains a transistor connected to a capacitor. The transistor contains, inter alia, two diffusion regions separated from one another by a channel controlled by a gate. One diffusion region is referred to as the drain region and the other diffusion region is referred to as the source region.
One of the diffusion regions is connected to a bit line, the other diffusion region is connected to the capacitor and the gate is connected to a word line. By applying suitable voltages to the gate, the transistor is controlled in such a way that a current flow between the diffusion regions through the channel is switched on and off.
The integration density is continuously increased by the advancing miniaturization of memory devices. The continuous increase in the integration density results in that the area available per memory cell decreases further and further. If the selection transistor is formed as a planar transistor, for example, then the lateral distance between the selection transistor and the trench capacitor consequently decreases further and further. That leads to a reduction of the blocking capability of the selection transistor, which blocks more poorly with decreasing channel length on account of the short-channel effect. The increased leakage currents discharge the trench capacitor prematurely, as a result of which the information stored in the trench capacitor and the memory cell is lost.
The short-channel effects are intensified by the outdiffusion of a buried strap. The buried strap is usually disposed in the trench capacitor above the conductive trench filling and serves for electrically connecting the conductive trench filling to a doping region of the transistor. In this case, an outdiffusion of dopant from the buried strap into the substrate and the adjoining doping region of the selection transistor is usually carried out, thereby forming the electrical contact. What is disadvantageous about a conventional buried strap is that it intensifies the short-channel effects that occur.
A further problem known from the prior art is that the doping region of the selection transistor is usually to be formed in monocrystalline silicon in order to avoid leakage currents through the selection transistor. Since the buried strap is usually formed from polycrystalline silicon which adjoins the monocrystalline silicon of the doping region of the selection transistor, at elevated temperatures crystal dislocations are formed in the monocrystalline silicon proceeding from the interface between polysilicon and monocrystalline silicon, and can lead to leakage currents through the selection transistor.
What is disadvantageous about an epitaxially grown buried strap is that crystal dislocations are formed at the transition between the silicon grown epitaxially in monocrystalline form and silicon grown in polycrystalline form. This defect formation leads to increased leakage currents in the selection transistor. During the further fabrication process of the DRAM, the dislocations move and can short-circuit the selection transistor.
Fabrication methods for DRAM memory cells having a trench capacitor and selection transistor are specified for example in U.S. Pat. Nos. 5,360,758, 5,670,805 and 5,827,765 and the reference by U. Gruening et al. title “A Novel Trench DRAM Cell with a Vertical Access Transistor and Buried Strap for 4 Gb/16 Gb”, IEDM, 1999.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a semiconductor memory cell and a method for fabricating the memory cell that overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, which enables an improved doping profile of the buried strap and avoidance of crystal defects in the selection transistor. With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a semiconductor memory having a trench capacitor and a selection transistor. The method includes providing a substrate having a substrate surface with a trench formed therein, forming an insulation collar in an upper region of the trench and on a sidewall of the trench, depositing a dielectric layer functioning as a capacitor dielectric on the insulation collar, providing a conductive trench filling in the trench, sinking the conductive trench filling into the trench to a first sinking depth, removing the dielectric layer from the insulation collar in a region above the first sinking depth, sinking the conductive trench filling into the trench to a second sinking depth, uncovering the substrate at the sidewall of the trench above the conductive trench filling resulting in an uncovered sidewall, growing an epitaxial layer on the uncovered sidewall of the trench, forming an intermediate layer on the epitaxial layer, introducing a dopant into the epitaxial layer, and completing the trench capacitor and the selection transistor.
One advantage of the epitaxially grown layer is that the dopant outdiffused from the buried strap has a shorter diffusion length in the epitaxially grown layer than in the adjoining bulk silicon in which the selection transistor is formed. This has the result that the dopant outdiffused from the buried strap does not diffuse right into the channel of the selection transistor, thereby preventing intensification of the short-channel effect in the selection transistor. The first intermediate layer has the advantage that crystal dislocations formed in the buried strap do not grow into the monocrystalline substrate in which the selection transistor is disposed. Crystal defects are thereby avoided at the doping region of the transistor, whereby it is possible to achieve an improved transistor with small leakage currents.
It is preferably provided that the epitaxially grown layer is disposed on the sidewall of the trench above the insulation collar in the direction of the substrate surface. This improves the dopant profile of the outdiffusion above the insulation collar.
Usually, a capacitor dielectric is disposed in the trench between the conductive trench filling and the substrate.
A further refinement of the invention provides for the selectively epitaxially grown layer (SEG: selective epitaxial growth) to have a facet having an angle of approximately 45 degrees relative to the substrate surface. The facet has the advantage that the electrical resistance between the doping region of the transistor and the conductive trench filling is reduced on account of the facet geometry. The facet is, for example, a natural crystal orientation of silicon.
A further refinement provides for the facet to be situated at the lower end of the epitaxially grown layer above the insulation collar. In particular, it is provided that a barrier layer is introduced in an annular gap formed by the facet and the upper edge of the insulation collar, which barrier layer prevents a diffusion of dopants to the sidewall of the trench. Since the thickness of the epitaxially grown layer decreases towards the upper and lower edges, it is advantageous to fill the annular gap which is produced at the lower edge and is formed by the facet and the upper edge of the insulation collar with a diffusion-blocking material before the trench filling is introduced, which is generally composed of polysilicon with dopants added to it, which can di
Grüning-Von Schwerin Ulrike
Gustin Wolfgang
Rongen Stefan
Schrems Martin
Strasser Rudolf
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Nguyen Van Thu
Smith Brad
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