Semiconductor memory capable of high-speed data erasing

Details Semiconductor memory capable of high-speed data erasing Semiconductor memory capable of high-speed data erasing

1988-11-30

1990-10-23

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Erase

365149, 365177, G11C 11409

Patent

active

049657690

ABSTRACT:
A semiconductor memory having a plurality of word lines, and a plurality of data lines arranged to intersect the word lines. Memory cells are arranged at nodes of the word lines and the data lines. Each of the memory cells has a field effect transistor and a capacitor. A word line multiple selection circuit is provided for selecting a plurality of the word lines. The multiple selection circuit simultaneously accesses all of the memory cells by selecting all the word lines of a memory array when a semiconductor memory is in a clear mode. In the clear mode a detector selects data lines of the memory array. A plate voltage control circuit controls a voltage at one plate of each of the capacitors in the memory cells. The plate control circuit changes a voltage at the plate to a preselected clear mode voltage when a semiconductor memory is in a clear mode. It is a feature of the invention that preselected data is written in the memory cells by data communication through the data lines during the clear mode. The preselected data includes at least one "1" data of the preselected data written in the memory cells. Subsequently to end the clear mode operation, the plate voltage control circuit changes the plate voltage for normal operations.

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Kawamoto et al., "A 288K CMOS Pseudostatic RAM", IEEE Journal of Solid-State Circuits, vol. SC-19, No. 5, Oct. 1984, pp. 619-623.

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