Semiconductor memory arrays

Details Semiconductor memory arrays Semiconductor memory arrays

1997-02-28

1998-04-07

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Precharge

365233, G11C 700

Patent

active

057372713

ABSTRACT:
Circuits and methods are disclosed for a row activation control logic for memory arrays. This invention utilizes a row activation control circuit and a NOR gate, in conjunction with a previously disclosed timing reference circuit, to allow the shortening of the row precharge time, yet insuring that the bitline is getting charged well enough without causing the chip to read wrong data at the next row activation. The circuits and methods disclosed can be applied to different types of dynamic random access memories.

REFERENCES:
patent: 4998222 (1991-03-01), Sussman
patent: 5185719 (1993-02-01), Dhong et al.
patent: 5315551 (1994-05-01), Hirayama
patent: 5357468 (1994-10-01), Satani et al.
patent: 5522064 (1996-05-01), Alderegula et al.
patent: 5563831 (1996-10-01), Ting

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