Semiconductor memory array with buried drain lines and...

Details Semiconductor memory array with buried drain lines and... Semiconductor memory array with buried drain lines and...

1999-05-10

2001-11-27

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S594000

Reexamination Certificate

active

06323089

ABSTRACT:

FIELD OF INVENTION
This invention generally relates to semiconductor memory circuits, and in particular, to an electrically erasable programmable read only memory circuit (EEPROM) that includes buried bitlines for decreasing the size and cost of manufacturing the memory circuit and processing methods therefor.
BACKGROUND OF THE INVENTION
Semiconductor memory array circuits, and specifically, electrically erasable programmable read only memories (EEPROMs), are rapidly growing in popularity today. They are extensively used in modern digital and computer systems for storing data and instructional codes that manipulate data to perform the desired functions.
Referring to
FIG. 1
, a block and schematic diagram of a prior art EEPROM memory array circuit
10
is shown with associated circuitry for addressing and performing memory operations on the memory array circuit. The EEPROM memory array circuit
10
comprises a plurality of memory cells arranged in an array orientation, including rows and columns of memory cells. Each memory cell consists of a field effect transistor (FET) having a drain (D), a source (S), and a gate (G), as it is conventionally known. The gate of an EEPROM memory cell FET typically consists of a floating gate (FG) and a control gate (CG). Some prior art EEPROM memory circuits further include an erase gate (EG) in addition to the floating and control gates (not shown in the prior art memory circuit of FIG.
1
). As it is well known, the floating gate typically is the portion of the memory cell that holds the data content in the form of stored electron charges. The control gate is used for addressing the memory cell in order to perform memory operations on the cell, including writing, erasing and reading operations.
As explained earlier, the memory cell FETs of the prior art EEPROM memory array circuit
10
are arranged in an array orientation, which includes rows and columns of memory cell FETs. The memory cell FETs within a row typically have their respective control gates (CG) connected in common by a conductive line, typically designated as the wordline. The memory cell FETs within a column typically have their respective drains (D) connected in common by another conductive line, typically designated as the bitline. Usually, the source (S) of each memory cell FETs are all connected in common, and is designated as the common source. Each memory cell typically includes its own individualized floating gate (FG). Although as drawn in
FIG. 1
the columns of the prior art EEPROM memory array
10
are shown to be horizontal, and the rows are shown to be vertical, the memory circuit
10
was drawn this way to schematically illustrate the structural orientation of the memory array, as will be explained in more detail later.
As it is conventionally known, the bitlines of the prior art EEPROM memory array
10
, designated herein as BL
1
sequentially through BLm, including a BLi which designates the bitline corresponding to the i-th column of memory cell FETs, are typically coupled to the outputs of a column address decoder/Y-Mux
14
. The wordlines, designated herein as WL
1
sequentially through WLn, including a WLj which designates the wordline corresponding to the j-th row of memory cell FETs, are coupled to the outputs of a row address decoder
12
. As it is conventionally known, the row and column address decoders
12
and
14
are employed for addressing a particular row and column of memory cell FETs that are both common to a selected memory cell FET for which a memory operation is to be performed on, such as a writing, erasing or reading operation. Also included is a memory operation circuit
16
used for performing memory operations on the memory cells of the array. The memory operation circuit
16
includes a sense amplifier
18
and output and input buffers
20
and
22
, as it is conventionally known.
Referring to
FIG. 2
, a structural and schematic diagram of a portion of the prior art EEPROM memory array
10
is shown. The portion shown includes memory cell FETs that are in rows common to wordlines WL(j−
2
) sequentially through WL(j+
3
), and memory cell FETs that are in column common to bitlines BL(i−
2
) sequentially through BL(i+
3
). Structurally, the memory cell FETs of the prior art EEPROM memory array
10
are formed within and on a silicon substrate
24
. The sources (S) of the memory cell FETs are formed as diffusion lines within the substrate
24
, and run parallel to the wordlines to connect in common the sources of memory cells in each of the rows. That is, the memory cell FETs that are within a row of memory cells have their sources connected in common by the source diffusion line, such as source diffusion lines SL(K−
1
), SL(K) and SL(K+
1
) shown in FIG.
2
. In addition, pairs of adjacent memory cell FETs along the bitline direction have common sources connected to their corresponding source lines. For example, as shown in
FIG. 2
, the memory cell FETs common to wordlines WL(j) and WL(j+
1
) have their sources connected in common by source diffusion line SL(k).
The floating gates (FGs) of the memory cell FETs of the prior art EEPROM memory array
10
are typically formed as islands of polycrystalline silicon formed over a portion over the FETs' channel in a split-gate type EEPROM, which herein is serving as an example, adjacent to respective diffused source lines. Each memory cell FET includes its own floating gate (FG) and is separated from the substrate by a thin oxide layer, as it is conventionally known.
The wordlines (WL
1
-WLn) of the prior art EEPROM memory cell FETs are formed as polycrystalline silicon conductive lines situated over the substrate
24
. Portions of each polycrystalline wordline are situated over respective memory cell FETs which form the control gates of FETs in a respective row of memory cells. In the split-gate configuration, a portion of the polycrystalline silicon control gates are formed over the portion of a respective channel that is not underlying a respective floating gate (FG), and is separated from the substrate by a thin oxide, as it is conventionally known. Another portion of the polycrystalline control gate (CG) is formed over a respective floating gate (FG) and is separated therefrom also by a thin oxide layer, as it is conventionally known.
The bitlines (BL
1
-BLm) of the prior art EEPROM memory array
10
are formed as metal lines deposited over the substrate
24
and over the other elements of the memory cell FETs, and are separated therefrom by an insulating oxide layer. The polycrystalline bitlines connect in common the drains (D) of memory cell FETs in respective columns, where these drains are formed as diffused region within the substrate
24
. In order to electrically connect the bitlines to the drains of the memory cell FETs, a contact needs to be made through an insulating layer and down to the diffused drain region of each memory cell FET. As it will be explained in more detail below, it is the size requirement of these contacts and the areas around the respective contacts that is an impediment to the further shrinking and densifying of the prior art EEPROM memory array circuit
10
.
Referring to
FIG. 3
, a plan view of a portion of the prior art EEPROM memory array
10
is shown. Specifically, four memory cell FETs are shown having common wordlines WL(j) and WL(+
1
), and common bitlines BL(i) and BL(i+
1
). As discussed above, each memory cell FET includes a control gate (CG) formed as a portion of the polycrystalline silicon wordline, and floating gate (FG) formed as an island of polycrystalline silicon. Adjacent pairs of memory cell FETs along the bitline direction have their respective sources connected in common by the diffused source line SL(k). As it is conventionally known, memory cell FETs are separated from adjacent memory cell FETs along the wordline direction by a field oxide layer (FOX). Notably though, each memory cell FET includes diffused drain regions connected to respective bitlines by way of a drain contact.
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