Semiconductor memory apparatus having refresh test circuit

Details Semiconductor memory apparatus having refresh test circuit Semiconductor memory apparatus having refresh test circuit

1999-08-30

2000-07-25

Hoang, Huan

Static information storage and retrieval

Read/write circuit

Testing

36523003, 365222, G11C 700

Patent

active

060943890

ABSTRACT:
A semiconductor memory apparatus having a refresh test circuit provided with a control unit, a write control unit, a row address buffer and column address buffer, a refresh address counter, a refresh control unit, a column decoder, a data input/output buffer, a plurality of sense amplifier arrays and a plurality of memory cell arrays, includes a refresh test control unit for receiving an address signal by the control of the control unit and controlling the refresh control unit, the row block decoder and the plurality of sense amplifier arrays. The apparatus screens refresh-related poor products by efficiently applying a disturb refresh test during a short period of time.

REFERENCES:
patent: 5959930 (1999-09-01), Sakurai
patent: 5987632 (1999-11-01), Irrinki et al.

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