Semiconductor memory apparatus

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

Reexamination Certificate

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Details

C365S189070, C365S193000

Reexamination Certificate

active

08031535

ABSTRACT:
A semiconductor memory apparatus includes an input buffering block configured to buffer an input signal transmitted from an input pin, a latch block configured to latch the input signal buffered by the input buffering block, a defect discriminating block configured to discriminate whether or not the input signal latched by the latch block is defective signal in response to a test mode signal, and a data output buffer configured to buffer an output signal of the defect discriminating block to transmit it to a data output pin, wherein the input signal is one of an input command signal and an input address signal.

REFERENCES:
patent: 5278803 (1994-01-01), Wanner
patent: 6408414 (2002-06-01), Hatada
patent: 6470467 (2002-10-01), Tomishima et al.
patent: 7057946 (2006-06-01), Fukuda
patent: 2006/0220672 (2006-10-01), Sato
patent: 1020000000990 (2000-01-01), None
patent: 1020070040745 (2007-04-01), None
patent: 1020070117855 (2007-12-01), None

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