Semiconductor memory apparatus

Details Semiconductor memory apparatus Semiconductor memory apparatus

2002-10-11

2004-07-06

Lam, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Multiplexing

C365S230020, C365S205000

Reexamination Certificate

active

06760260

ABSTRACT:

FIELD OF INVENTION
This invention relates to a semiconductor memory.
RELATED APPLICATIONS
This application claims the benefit of the Oct. 12, 2001 priority date of German application 101 50 498.5-53.
BACKGROUND
Note: signal and line designations “bar_xy” in the description and in the claims correspond to the signal designations “xy” with a horizontal line above them in the drawings.
Semiconductor memory apparatuses are known which comprise a multiplicity of memory cell arrays. Each memory cell array has an associated multiplicity of local sense amplifiers which receive, assess and amplify the data which are read from the memory cell array. The sense amplifiers are arranged in a sense amplifier row above or below the memory cell array. Each sense amplifier comprises, in addition to the actual amplifier device, a pair of selection transistors which allow one sense amplifier from a plurality of adjacent sense amplifiers to be selected to pass its information to a differential data transmission line. This allows, by way of example, a block of 32 sense amplifiers to be constructed which use 32 selection lines CSL (column select line) to forward their respective information to a common differential pair of data transmission lines LDQ, bar_LDQ. In this context, the respective signal A, B, C . . . is output to the line LDQ, and the inverse of the respective signal bar_A, bar_B, bar_C . . . is output to the line bar_LDQ.
FIG. 4
shows a basic sketch of selection transistors
1
for sense amplifiers based on the prior art. The two respective selection transistors
1
for a sense amplifier are respectively formed from two diffusion regions
2
and a common gate
3
.
One selection transistor
1
for each sense amplifier is connected for signaling purposes to the data transmission line LDQ, and the other selection transistor
1
for each sense amplifier is connected for signaling purposes to the data transmission line bar_LDQ. The sense amplifier row containing selection transistors
1
is wider than the memory cell array itself, however, the result of which is that the available surface area on the semiconductor apparatus cannot be utilized in optimum fashion.
SUMMARY
It is thus an object of the present invention to provide a semiconductor memory apparatus which allows better use of the available resources.
This object is achieved by a semiconductor memory apparatus having the features specified in claim
1
. Preferred embodiments are covered by the dependent claims.
The invention provides a semiconductor memory apparatus or memory chip or memory module, comprising:
at least one memory cell array having a multiplicity of data lines or bit lines,
a multiplicity of local amplifiers or local sense amplifiers for amplifying signals or data transmitted to and/or from the memory cell array, where the multiplicity of local amplifiers can be connected for signaling purposes to the multiplicity of data lines,
each amplifier has precisely one uniquely associated data line, and at least two amplifiers and the associated data lines respectively form a group;
where each amplifier comprises at least two selection transistors for selecting an amplifier from a group of amplifiers,
where the at least two selection transistors for an amplifier respectively comprise two intrinsic diffusion regions and a common control electrode or gate, and
where adjacent selection transistors for adjacent amplifiers use a diffusion region jointly.
The fact that adjacent amplifiers use a respective diffusion region jointly means that the surface area needed for arranging the amplifiers can advantageously be reduced. This allows a more compact design for the semiconductor memory apparatus. In addition, the unique association between each data line and each amplifier allows an increased reading and writing speed to be achieved. Such amplifiers are also referred to as “dedicated amplifiers”.
Preferably, the local amplifiers comprise sense amplifiers, “dedicated sense amplifiers”, for amplifying data which are read from the memory cell array.
In one preferred embodiment, the semiconductor memory apparatus comprises at least one pair of data transmission lines, where each data transmission line in a pair of data transmission lines can respectively be connected for signaling purposes to all the amplifiers in a group. This allows the number of data transmission lines needed to be advantageously reduced.
Preferably, the selection transistors using a common diffusion region use a connecting line for the respective data transmission line jointly. This allows the available surface area to be utilized even more advantageously, since only approximately half the number of connecting lines are now needed as compared with the conventional case.
In addition, preferably, one data transmission line in a pair of data transmission lines is used to transmit the respective signal to be transmitted, and the other data transmission line in the pair of data transmission lines is used to transmit the inverse of the respective signal to be transmitted.
In one preferred embodiment, the semiconductor memory device also comprises a multiplex device for sequentially transmitting data from the data lines in a group. This allows error-free transmission of the data from and to the semiconductor memory apparatus to be reliably ensured. Preferably, the multiplex device comprises a multiplicity of selection lines, with each data line having an associated selection line.
Preferably, 32 amplifiers and the associated data lines form a group.
With further preference, at least one memory cell array comprises 1024 data lines.
Preferably, the semiconductor memory apparatus comprises 64 memory cell arrays.
In one preferred embodiment, the semiconductor memory apparatus comprises an address allocation device for allocating internal addresses to external addresses in a memory cell array. This allows an internal addressing order which is altered in the memory cell array to be adjusted or scrambled such that it does not appear externally.
Other objects, features and advantages of the present invention will become obvious from a detailed description of the present invention with reference to the accompanying drawings, in which:


REFERENCES:
patent: 5406525 (1995-04-01), Nicholes
patent: 5666319 (1997-09-01), Okamura

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