Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2001-01-17
2003-04-01
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Signals
C365S189011, C365S205000, C365S207000
Reexamination Certificate
active
06542417
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory. More particularly, it relates to a data bus configuration of a semiconductor memory, such as a DRAM, and data read/write operations of a semiconductor memory.
The increase in memory capacity of recent semiconductor memories has resulted in an increase in the chip area of the semiconductor memories.
Such a semiconductor memory has a plurality of banks. Write data is provided to each bank through a global data bus (GDB). Further, read data is output from each bank through the global data bus. Each bank has a local data bus (LDB).
FIG. 1
is a schematic circuit diagram of a first prior art example of a semiconductor memory
100
and illustrates the connection between a local data bus and memory cells.
The semiconductor memory
100
has a cell array
1
, which includes a plurality of word lines (two shown in the drawing) WL
1
, WL
2
and a plurality of bit line pairs (one pair shown in the drawing) BL, /BL. A memory cell
2
is connected to a node between the word line WL
1
and the bit pairs BL, /BL. Another memory cell
2
is connected to a node between the word line WL
2
and the bit pairs BL, /BL. The bit line /BL is driven by a logic signal that is in inverse relationship with a signal that drives the bit line BL. In other words, the bit line pair BL, /BL is driven by complimentary signals.
The potentials of the word lines WL
1
, WL
2
are controlled by a row decoder (not shown) in correspondence with read or write operations. The row decoder functions in response to an external command.
The bit line pair BL, /BL is connected to I/O terminals T
1
, T
2
of a sense amplifier
5
via transfer gates
3
,
4
, respectively. The I/O terminals T
1
, T
2
are connected to data bus lines DB, /DB of a local data bus via column gates
6
,
7
, respectively.
With reference to
FIG. 2
, during a read mode, a signal of the word line WL
1
goes high in response to a read command received from an external device. This transfers the data stored in the memory cells
2
to the bit line BL. In response to a control signal BT, the data of the bit line BL is transferred to the sense amplifier
5
via the transfer gate
3
. Then, the sense amplifier
5
, which is activated by a read command, drives the bit line pairs BL, /BL in accordance with the transferred data to a predetermined potential in a complementary manner. The column gates
6
,
7
are activated when a column selection signal CL goes high. This causes the potential at the data bus line pair DB, /DB to be the same as the potential at the bit line pair BL, /BL. In this manner, the data of the memory cells
2
is transferred to the data bus line pair DB, /DB.
With reference to
FIG. 3
, during a write mode, the signal of the word line WL
1
goes high in response to a write command received from the external device. As a result, data is read from the memory cells
2
. Subsequent to the activation of the sense amplifier
5
, an activation of the column gates
6
,
7
in response to the column selection signal CL transfers the data from the data bus line pair DB, /DB to the sense amplifier
5
via the columns gates
6
,
7
. The sense amplifier
5
drives the bit line pair BL, /BL in accordance with the data. This writes the data transferred from the data bus line pair DB, /DB to the memory cells
2
.
In the above prior art example, one bit of data is transferred by the two complementary data bus lines DB, /DB. This increases the circuit area and cost of the semiconductor memory.
To solve this problem, a second prior art example of a semiconductor memory
200
having a single-phase data bus configuration has been proposed. The semiconductor memory
200
includes a single-phase local data bus DB. The data bus DB is directly connected to a bit line BL. An inverting latch
8
is connected between the bit line BL and a bit line /BL. The inverting latch
8
inverts the data transferred through the data bus line DB and provides the inverted data to the bit line /BL. The two bit lines BL, /BL are driven in a complementary manner.
In the second prior art example, the number of data bus lines forming a local data bus is less than that of the first prior art example. Thus, the wiring area is smaller that the first prior art example. However, the second prior art example requires an inverting latch
8
for each bit line pair BL, /BL. This increases the circuit area.
The inverting latch
8
may be eliminated. In such a case, however, even when high potential data is applied to the data bus DB during the write operation, the high potential data would not be transferred to the sense amplifier
5
due to the drive capability of the sense amplifier
5
and the column gate
6
.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory having a reduced circuit area.
To achieve the above object, the present invention provides a semiconductor memory including a plurality of memory cells and having a write mode. The semiconductor memory includes a plurality of pairs of bit lines connected to the memory cells and a plurality of sense amplifiers, each having a first I/O terminal and a second I/O terminal which are connected to an associated pair of the bit lines. The semiconductor memory further includes a plurality of column selection gates, each connected to the first I/O terminal of an associated one of the sense amplifiers, a data bus connected to the column selection gates, and a control circuit connected to the sense amplifiers. The control circuit controls the sense amplifiers and the column selection gate, so that selected column selection gate turns on before the sense amplifiers are activated during the write mode.
The present invention further includes a method for controlling a semiconductor memory including a plurality of memory cells, a plurality of pairs of bit lines connected to the memory cells, a plurality of sense amplifiers, each having a first I/O terminal and a second I/O terminal which are connected to an associated pair of the bit lines, a plurality of column selection gates, each connected to the first I/O terminal of an associated one of the sense amplifiers, and a data bus connected to the column selection gates. The semiconductor memory is operated in a write mode and a read mode. Data is written to the memory cells in the write mode, and data is read from the memory cells in the read mode. The method includes selectively operating the column selection circuit to apply a potential of the data bus to the first I/O terminal of a selected one of the sense amplifiers during the write mode, and activating the selected one of the sense amplifiers during the write mode.
The present invention further includes a method for writing a semiconductor memory. The method includes selectively operating column selection circuits to apply a potential of a data bus to a first I/O terminal of a selected one of sense amplifiers, then activating the selected one of the sense amplifiers.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
REFERENCES:
patent: 5555210 (1996-09-01), Kato
patent: 5796668 (1998-08-01), Seo et al.
patent: 6031785 (2000-02-01), Park et al.
patent: 6222787 (2001-04-01), Yoon et al.
patent: 6301191 (2001-10-01), Ooishi
patent: 2-226581 (1990-09-01), None
patent: 7-244986 (1995-09-01), None
Arent Fox Kintner & Plotkin & Kahn, PLLC
Dinh Son T.
Fujitsu Limited
LandOfFree
Semiconductor memory and method for controlling the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory and method for controlling the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory and method for controlling the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3010110