Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1985-07-19
1986-05-27
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
365230, G11C 1140, G11C 1300
Patent
active
045920222
ABSTRACT:
A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the data lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.
REFERENCES:
patent: 4507759 (1985-03-01), Yasui et al.
Ikuzaki Kunihiko
Kawamoto Hiroshi
Masuda Hiroo
Shimohigashi Katsuhiro
Fears Terrell W.
Hitachi , Ltd.
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