Semiconductor memory

Details Semiconductor memory Semiconductor memory

1988-10-11

1990-01-09

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Precharge

365205, G11C 700

Patent

active

048932779

ABSTRACT:
A dynamic RAM is arranged such that a common data line in each of the non-selected ones of the divided memory arrays is connected to a pair of common source lines of a sense amplifier corresponding to the memory array concerned, whereby the potential of the common data line is set at a medium level which is substantially equal to the potential of the data lines by utilizing the medium potential of the pair of common source lines and a relatively large parasitic capacity thereof, thereby maintaining the data lines at the half-precharge level. The pair of common source lines are shorted to each other during the non-select period of the memory arrays, so that the common source lines have a medium level which is substantially equal to the half-precharge level of the data lines.

REFERENCES:
patent: 4112508 (1978-09-01), Itoh
patent: 4368529 (1983-01-01), Furuyama
patent: 4601017 (1986-07-01), Mochizuki et al.
patent: 4780852 (1988-10-01), Kajigaya et al.
H. Kawamoto et al., "A 288 Kb CMOS Pseudo SRAM", 1984 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 276-277.

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