Semiconductor memory

Details Semiconductor memory Semiconductor memory

1985-10-21

1987-09-15

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365 51, 365 63, G11C 700

Patent

active

046944281

ABSTRACT:
In a semiconductor memory, a memory cell array is divided into a plurality of sub arrays in a direction perpendicular to word lines. In each sub array sub word lines and bit lines are disposed to intersect each other and memory cells are disposed at all their intersections. Two different sub arrays constitute a unit cell array. The sub word line connected to a cell transistor in one of or the first the sub arrays of the unit cell array is connected to a first main word line and a second main word line which is not connected to the cell transistor in the first sub array is passed therethrough for connection with the sub word line of the other or second sub array in the unit cell array.

REFERENCES:
patent: 4551820 (1985-11-01), Matsuura
patent: 4615021 (1986-09-01), Yoshida et al.

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