Static information storage and retrieval – Read/write circuit – Including signal clamping
Patent
1995-09-25
1996-11-12
Dinh, Son T.
Static information storage and retrieval
Read/write circuit
Including signal clamping
36518911, 365190, 365202, 365203, G11C 700
Patent
active
055746870
ABSTRACT:
There is disclosed a rapidly and correctly readable semiconductor device wherein a clamping transistor (Pcr.sub.-- 0) having a threshold voltage (Vthp) precharges a pair of bit lines (BIT.sub.-- 0, BIT.sub.-- 1) at a precharge potential (VDD-.vertline.Vthp.vertline.) when transistors (Pprc.sub.-- 0, Pprc.sub.-- 1) are conducting, and a write circuit (3) includes a clamping transistor (Pcr.sub.-- 1) having the same threshold voltage (Vthp) as the clamping transistor (Pcr.sub.-- 0), and inverters (23, 24) responsive to input data (DIN.sub.-- 0, DIN.sub.-- 1) for outputting signals which are "H" at the precharge potential (VDD-.vertline.Vthp.vertline.) and "L" at the ground potential to a pair of write input lines (WD.sub.-- 0, WD.sub.-- 1), respectively.
REFERENCES:
patent: 4730279 (1988-03-01), Ohtani
patent: 5068830 (1991-11-01), Plants et al.
patent: 5119335 (1992-06-01), Nozaki
patent: 5309401 (1994-05-01), Suzuki et al.
1993 IEEE International Solid-State Circuits Conference Tech. Papers, pp. 242-243, Feb. 26, 1993, Larry R. Fenstermaker, et al., "A Low-Power Generator-Based FIFO Using Ring Pointers and Current-Mode Sensing".
1990 Symposium on VLSI Circuits Digest of Technical Papers, pp. 115-116, Kunio Uchiyama, et al., "Architecture and Design of a Second-Level Cache Chip with Copy-Back and 160MB/s Burst-Transfer Features".
Dinh Son T.
Mitsubishi Denki & Kabushiki Kaisha
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