Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2002-03-27
2004-06-22
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S230030, C365S220000, C365S236000, C365S239000
Reexamination Certificate
active
06754126
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a dynamic RAM which requires regular refresh operation of memory cells. Particularly, the present invention relates to a technology to automatically perform the refresh operation in its interior without the need for a refresh request from the exterior.
2. Description of the Related Art
A DRAM is suitable to attain high integration because its memory cells can be structured small. However, the DRAM requires the refresh operation in order to hold data stored in the memory cells. It is necessary to perform the refresh operation regularly on each of the memory cells. When the refresh request is generated, the refresh operation should be performed while taking priority over read operation and write operation.
In a system on which the DRAM is mounted, for example, a memory controller which controls the DRAM supplies a refresh command to the DRAM while taking priority over a read command (or a write command), when the refresh request is generated from its own refresh timer.
Meanwhile, an SRAM does not require the refresh operation, contrary to the DRAM. However, since a number of elements constituting the one-bit cell is larger than that of the DRAM, it is disadvantageous to attain large capacity.
In other words, the refresh operation has to be performed when necessary as long as a DRAM (dynamic random access memory) memory core is used. An operation area being in refresh operation cannot be accessed. As a result of this, when the refresh operation and an access request come at the same time, the access should be suspended until the completion of the refresh operation.
If the DRAM is operated as the SRAM (static random access memory) to which the refresh request is not inputted from the exterior, the refresh request needs to be regularly generated in its interior. When an access request is supplied from the exterior at this point, since the requested access is performed after the refresh operation, performing an actually single access appears to take a time equivalent to performing two operations of the memory core.
In a conventional DRAM, there is a disadvantage that its control increases in complexity because the memory controller controls the refresh operation as well. Further, since it is impossible to perform the read operation and the write operation during the refresh operation, there is a disadvantage that a data transfer rate decreases as compared with the SRAM.
Meanwhile, in the SRAM, it is difficult to attain the large capacity as described above, and further, there is a disadvantage that its chip cost is highly expensive as compared with the DRAM because its memory cells are large.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory having both large capacity of a DRAM and usability of an SRAM.
It is another object of the present invention to provide the semiconductor memory which promptly responds to a request for read operation from the exterior of the memory, and whose data transfer rate is high.
It is still another object of the present invention to perform an external access in an access time taken for a single operation of a memory core, even when a refresh operation and an external access request conflict with each other.
According to one of the aspects of the semiconductor memory of the present invention, the semiconductor memory comprises a plurality of first memory blocks for storing data and a second memory block for storing data to reproduce the data stored in the first memory blocks. For example, the second memory block stores a parity bit of the first memory blocks as data. A first command generator receives a command from the exterior of the memory and generates a read command or a write command for accessing the first memory blocks, according to the received command. A second command generator generates a second command for accessing the first memory blocks or the second memory block.
When the read command and the second command access the same first memory block, that is, when the read command and the second command conflict with each other, a read control circuit accesses the first memory block according to the second command. Further, in order to operate in accordance with the read command, the read control circuit reproduces read data, which should be originally read from the first memory blocks, by using the data stored in the second memory block and the other first memory blocks. Hence, read operation time is not extended even when the read command and the second command conflict with each other. Namely, generation of the second command does not affect the read operation.
When the write command and the second command access the same first memory, a write control circuit performs operations according to commands in order in which the commands have been received. For example, when generation of the second command comes earlier than supply of the write command, the write control circuit first accesses the first memory block according to the second command, and thereafter performs write operation. At this time, the write operation in the semiconductor memory delays than usual, but changing supply timings of an address, write data, and the like from the exterior is not necessary. Hence, the generation of the second command does not affect the write operation.
As described above, users of the semiconductor memory can perform the read operation and the write operation without recognizing the conflict between the second command generated inside the semiconductor memory and the read and write commands supplied by the users. This makes it possible to provide a user-friendly semiconductor memory.
According to another aspect of the semiconductor memory of the present invention, the first and second memory blocks are structured of volatile memory cells from which data disappears over time. The second command is a refresh command generated periodically for performing refresh operation of the memory cells. Therefore, the users can use the semiconductor memory without any recognition of the refresh. For example, applying the present invention to the DRAM makes a refresh controller unnecessary in a system on which the DRAM is mounted. In other words, the users can use the DRAM in much the same way as the SRAM.
According to another aspect of the semiconductor memory of the present invention, an external write cycle, as a minimum interval between supplies of the write command, is set to be longer than an internal write cycle as actual write operation time to the first and second memory blocks. A refresh cycle can be inserted without fail while the write command is supplied a plurality of times. Hence, it is possible to prevent the data held in the memory cells from being destroyed, even while the write command is supplied many times. As a way of example, in a semiconductor memory of a clock synchronous type, when the external write cycle is set to n clock cycles (n is an integer equal to or greater than 1), the internal write cycle is set to n−0.5 clock cycles. In this case, when the refresh cycle is 3.5 clock cycles, one refresh cycle can be inserted during seven write operations.
According to another aspect of the semiconductor memory of the present invention, when the internal write cycle is set to n−0.5 clock cycles, every time the write command or the refresh command is supplied, a cycle switching circuit alternately operates first and second cycle generators to operate in synchronization with a first edge and a second edge of an external clock, respectively. The first cycle generator generates a first timing signal for performing an internal operation cycle in synchronization with the first edge of the external clock. The second cycle generator generates a second timing signal for performing the internal operation cycle in synchronization with the second edge of the external clock. The two cycle generators are used alternately to perform the write operation or the refresh operation, by which facilitates the control of
Bando Yoshihide
Fujieda Waichiro
Fujioka Shin-ya
Hara Kota
Kobayashi Hiroyuki
Arent Fox PLLC.
Dinh Son T.
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