Semiconductor memory

Details Semiconductor memory Semiconductor memory

1999-02-23

2001-05-15

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Precharge

C365S205000

Reissue Patent

active

RE037176

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory and, more particularly, to a technique useful for a half-precharge type dynamic RAM (random-access memory).
In a dynamic RAM having a memory capacity, e.g., 1M bits, each of the memory cells has a relatively small size, and an exceedingly large number of memory cells are connected to each of the data lines. In accordance with these circumstances, the relationship between the capacity Cs of the storage capacitor of each memory cell and the floating capacity (data line capacity) Co of each data line, i.e., the ratio Cs/Co, becomes an exceeding small value. In consequence, a data signal applied to the data line from a memory cell, that is, a potential change applied to the data line in accordance with the amount of charge stored in the capacitor Cs, undesirably becomes an exceedingly minute value.
To overcome this problem, a dynamic RAM having the following arrangement is proposed in U.S. patent application Ser. No. 380,409, filed May 20, 1982, Ito et al. According to this technique, in order to ensure a desired read level from each memory cell, each data line is divided into a multiplicity of portions, that is, a memory array is divided into a multiplicity of regions in the direction of the data lines, thereby reducing the number of memory cells connected to each data line in each of the divided memory array regions and thus maintaining the ratio Cs/Co at a desired value.
SUMMARY OF THE INVENTION
The present inventors have examined the following techniques for the purpose of increasing the scale of integration of a dynamic RAM of the type in which each data line is divided, of simplifying the arrangement of such RAM, and of lowering the power consumption thereof. First, to increase the scale of integration, a common data line selecting signal line is employed, that is, a select signal for data lines in each of the divided memory arrays is formed by a single column address decoder. To simplify the arrangement of the memory arrays and lower the power consumption, the half-precharge method (dummy-cellless method) is adopted. The half-precharge method is mentioned in ISSCC (IEEE International Solid-State Circuits Conference)
84
DIGEST OF TECHNICAL PAPERS, p. 276 to p. 277. For lowering the power consumption, a sense amplifier in the one of the divided memory arrays in which a memory cell to be selected is present is operated alone.
The present inventors have found that the following problems arise when the above-described techniques are adopted. When a select signal for selecting one of the data lines in a plurality of divided memory arrays is formed by a common column address decoder, one data line in each of the non-selected memory arrays is undesirably connected to the common data line. The data line holds the above-described half-precharge level, whereas the common data line has a potential higher than the potential of the data line. Since the data line has a relatively small capacity Co as a result of the division of it, the potential of the data line is greatly fluctuated by the connection with the common data line. In consequence, during the read operation from the selected memory cell connected to the data line at the subsequent timing, level imbalance may occur between the pair of data lines, or the operating point of the associated sense amplifier is biased to a low-sensitivity region, resulting in an erroneous read operation.
Accordingly, it is an object of the present invention to provide a semiconductor memory so designed that the scale of integration is increased, and the operation is stabilized.
It is another object of the present invention to provide a dynamic RAM so designed that the scale of integration is increased, while the power consumption is lowered, and yet the operation is stabilized.
The above and other objects, novel features and advantages of the present invention will become clear from the following description of the preferred embodiment thereof, taken in conjunction with the accompanying drawings.
A brief summary of a representative embodiment of the novel techniques disclosed in this application is as follows. Each of the common data lines in the nonselected ones in the divided memory arrays and a pair of common source lines of the associated sense amplifier are connected together. The pair of common source lines are shorted to each other during a nonselect period, so that they have a medium level which is substantially the same as the half-precharge level of the data lines. Making use of the medium potential of the common source lines and a relatively large parasitic capacity thereof, the potential of the common data line is set at a medium level which is substantially the same as that of the data lines, whereby the data lines are maintained at the half-precharge level.


REFERENCES:
patent: 4112508 (1978-09-01), Itoh
patent: 4368529 (1983-01-01), Furuyama
patent: 4601017 (1986-07-01), Mochizuki et al.
patent: 4646267 (1987-02-01), Shimohigashi et al.
patent: 4660180 (1987-04-01), Tanimura et al.
patent: 4780852 (1988-10-01), Kajigaya et al.
H. Kawamoto et al., “A 288 Kb CMOS Pseudo SRAM”, 1984 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 276-277.

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