Semiconductor memory

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

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Details

365230, G11C 1140, G11C 1300

Patent

active

047394978

ABSTRACT:
A semiconductor memory is provided which includes a plurality of data lines, a plurality of word lines which are arranged so as to intersect the plurality of data lines, and a plurality of memory cells which are respectively disposed at intersection points between the plurality of data lines and the plurality of word lines. A row decoder selects at least one from among the plurality of word lines, while a column decoder generates a signal for connecting one of the plurality of data lines to an input/output line. A plurality of wiring leads are also provided which are formed of a conductor layer different from conductor layers constituting the plurality of data lines and the plurality of word lines and which are arranged so as to intersect the plurality of data lines.

REFERENCES:
patent: 3803554 (1974-04-01), Bock et al.
patent: 4351034 (1982-09-01), Eaton et al.

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