Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
1999-06-21
2001-03-06
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Precharge
C365S204000, C365S185250
Reexamination Certificate
active
06198678
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor memories and in particular, although not exclusively, to semiconductor read only memories.
DESCRIPTION OF THE RELATED ART
Traditionally, semiconductor read only memories (ROMs) have been designed for applications either where device density was more important than operating speed, or where operating speed was more important than device density. These two requirements have resulted in two different approaches to the design of ROMs and their sensing arrangements.
Where operating speed is of lesser importance, a digital logic approach to sensing memory core contents has been sufficient. Inherent in large ROMs is the presence of large capacitive loads on both bitlines and wordlines. Such loads require relatively long periods of time to allow slow moving voltage signals to propagate to the Q outputs. It is common for an inverter to be used to boost the bitline or mux output signals for the Q outputs. Where speed is more important, a number of smaller ROMs are generally used. Smaller ROMs are able to operate at higher speeds because bitline and wordline loads are smaller.
A number of approaches have been used to achieve higher operating speeds in larger ROMs. One such approach splits ROMs into smaller blocks of ROM which are connected in parallel. This approach results in smaller wordlines and bitlines but results in an inefficient device layout, and many circuits in each block of ROM necessarily are duplicated.
A second approach uses special coding techniques in ROM cells to reduce memory core area and internal signal propagation delays. This approach adds complexity to the ROM, which is often considered to be too great a pay off for the benefits achieved. Where ROM area is less critical, a third approach uses dual bit memory cells in the ROM core, to increase signal strength prior to sensing. Here, the bitline pair associated with each memory cell provides complementary signals to the sense amplifier in much the same way as a random access memory (RAM). The increased signal strength, i.e., larger amplitude signals, allows access times to be reduced. The fourth approach uses what can be described as a hybrid of a single and a dual bit memory cell to provide signals to a sense amplifier. In this approach, a reference voltage signal which is of an amplitude half way between a logic one and a logic zero is applied to the second input of the sense amplifier, with the first input being provided by the memory cell.
A conventional ROM according to the above mentioned fourth approach is shown in
FIG. 1
, in which first to fourth memory cell transistors
11
to
14
are connected each to one of wordlines wl<
1
> and wl<
0
> and to one of bitlines bl<
0
> and bl<
15
>. These transistors form part of a large array of memory cell transistors, typically 256k or 512k by 16 columns of transistors per bit by 8 bits per word in size, each similarly connected to a bitline and to a wordline. Only the four memory cell transistors
11
-
14
are shown for simplicity. The transistors
11
and
14
have their third electrode ground connected, whereas the transistors
12
and
13
do not. Dummy transistors
15
and
16
are connected, in a manner similar to the transistors
11
-
14
connections to the bitlines bl<
0
> and bl<
15
>, to a dummy bitline dbl. The bitlines bl<
0
>, bl<
15
> and dbl are selectively connected to supply voltage by respective ones of precharge transistors
17
,
18
and
19
. Bitlines bl<
0
> and bl<
15
> are selectively connected to a first sense amplifier input line mbll by respective ones of column decode logic and mux circuits
20
and
21
. The column decode logic and mux circuits
20
and
21
provide connection of their respective bitline bl<
0
> or bl<
15
> to the line mbll only in the presence of appropriate column select signals on a predecoded address bus line pradc. Only one of the bitlines bl<
0
> and bl<
15
> is selected at any one time. The bitline dbl is connected to a second sense amplifier input line mblr by a matching transistor
22
. A dummy memory cell transistor
23
is connected between the bitline dbl and ground.
Connected between the lines mbll and mblr are first and second equalization transistors
24
and
25
. Clamp transistors
26
and
27
connect respective ones of the lines mbll and mblr to supply voltage in dependence on the voltage present on their respective line mbll or mblr. The transistors
26
and
27
act as weak dc clamps, pulling the lines mbll and mblr to supply voltage when these lines are not driven. Transistors
28
,
29
,
30
and
31
are connected to form a sense amplifier, in a current mirror configuration. A sense amplifier output is taken from the connection between the sense amplifier transistors
28
and
30
.
A typical timing diagram is shown in
FIG. 2. A
received address is clocked through decode logic (not shown), which identifies a particular row and column, i.e., a particular wordline and bitline, of the memory core. The rising edge of the clock signal enables the precharge transistors
17
to
19
to pre-charge each of the bitlines bl<O>, bl<
15
> and dbl, and enables the equalization transistors
24
and
25
to equalize the lines mbll and mblr. At some time after this clock signal rising edge, the address decode logic circuit (not shown) applies signals to select appropriate ones of the wordlines and bitlines. Logic circuits (not shown) operate on detection of the wordline wl<
1
> or wl<
0
> and bitlines bl<
0
> or bl<
15
> having been selected and the bitlines having become charged to supply voltage, to invert the pre-charge and equalization signals applied to the transistors
17
to
19
and
24
and
25
.
The ones of the memory cells transistors
11
to
14
which are both enabled by virtue of a signal on their respective wordline and are connected to ground potential will cause discharging of their respective bitline. All other memory cell transistors will not effect any discharge of their respective bitline, except by intrinsic leakage. The switching of the dummy memory cell transistor
23
by the address decode logic (not shown) at the same time as the wordline selection causes discharge of the bitline dbl to ground potential. The dummy memory cell transistor
23
is always selected when any wordline is selected. This discharge occurs at half the rate of any other bitline which is being discharged. As the bitline bl<
0
> or bl<
15
> is connected to the line mbll through its respective column decode and mux logic circuit
20
or
21
and the dummy bitline dbl is connected to the line mblr through the transistor
22
, a divergence of the voltages on respective ones of the lines mbll and mblr will occur. This divergence is detected and amplified by the sense amplifier formed by transistors
28
to
31
. The sense amplifier thus provides a sense output signal which is indicative of the sense of the voltage signal on the line mbll compared to that of the voltage signal on the line mblr, which is thus representative of the state of the selected memory cell transistor
11
to
14
.
The sense output signal of the sense amplifier is propagated to and then buffered by a buffer (not shown) before being passed as the Q output. The buffer (not shown) introduces a slight delay.
In this ROM, non selected bitlines which are associated with a ground connected memory cell transistor in the selected row, even though they are not selected bitlines, will be discharged to ground.
The fact that each of the bitlines bl<
0
>, bl<
15
> and dbl are pre-charged before each read operation and around half of them are discharged at the end of each operation (assuming 50% ones and 50% zeros in any given row of a memory core) means that the
FIG. 1
ROM has quite high current consumption. Leakage of charge from the bitlines through the p-n leakage and sub-leakage effects intrinsic in memory cell transistors increases further the
Alan Martin
Albon Richard
Johnston David
Kirschstein et al.
Mitel Semiconductor Limited
Nelms David
Yoha Connie C.
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