Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-09-19
2004-07-20
Nguyen, Thanh (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000, C438S254000, C438S396000, C438S397000
Reexamination Certificate
active
06764896
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a capacitor.
2. Description of the Background Art
In a semiconductor device having a capacitor, such as DRAM (dynamic random access memory), since the capacitor capacitance does not response to the scaling law of high integration only by improving the capacitor structure, it is now considered to use materials of high dielectric constant, such as Ta
2
O
5
, (Ba, Sr)TiO
3
, Pb(Zr, Ti)O
3
, Pb(La, Ti) O
3
and SBT (SrBi
2
Ta
2
O
9
) as a dielectric to form a capacitor insulating film.
Further, as to a nonvolatile memory, ferroelectric memory utilizing polarization reversal of ferroelectrics is being developed.
In a case where a capacitor insulating film is formed of a material of high dielectric constant such as above, a capacitor electrode is generally formed mainly of a platinum-group element or an oxide of a platinum-group element.
Since the platinum-group element generally has a characteristic of low vapor pressure in a compound, an etching with ions of high energy, i.e., sputter etching is used in electrode formation. This method is a physical etching, and has problems that the selection ratio of mask material and workpiece is small, that the etching section has a tapered shape and microfabrication is difficult.
Then, a technique such as reactive ion etching using chemical etching method as well as physical etching with the wafer temperature kept high and the vapor pressure of reactive compound raised higher has been considered. This method uses a heat-resistant material such as a silicon oxide film, a silicon nitride film and a titanium nitride film, i.e., a hardmask as a mask material for electrode formation.
Hereafter, a background-art manufacturing method using reactive ion etching will be discussed, referring to cross sections of
FIGS. 15
to
21
showing the manufacturing process step by step.
First, in the step of
FIG. 15
, a silicon substrate
1
is prepared and an isolation insulating film
3
which electrically isolates elements and defines an active region which is to become an element formation region is formed. On the active region defined by the isolation insulating film
3
, a gate insulating film
4
and a gate electrode
5
of a MOS transistor are selectively formed. Then, an impurity diffusion layer
2
which is to become a source/drain layer is selectively formed in a main surface of the silicon substrate
1
with the gate electrode
5
used as a mask.
After that, an interlayer insulating film
6
is so formed on the silicon substrate
1
as to completely cover the MOS transistor. At this time, a contact plug
7
(bit line contact) connected to a predetermined impurity diffusion layer
2
and a bit line
8
electrically connected to the predetermined impurity diffusion layer
2
through the contact plug
7
are formed in the interlayer insulating film
6
.
After forming a silicon nitride film
11
on the interlayer insulating film
6
as an etching stopper, a plurality of contact plugs
10
(storage node contacts) penetrating the interlayer insulating film
6
and the silicon nitride film
11
to be connected to the predetermined impurity diffusion layer
2
are formed. Further, the contact plugs
7
and
10
are each formed of a conductor such as polysilicon.
Next, in the step of
FIG. 16
, a platinum film
12
and a silicon oxide film
13
are formed in this order on the silicon nitride film
11
. After that, a resist mask RM
1
which is so patterned as to correspond to a pattern of a capacitor lower electrode (storage node) is formed on the silicon oxide film
13
.
Next, in the step of
FIG. 17
, the silicon oxide film
13
is patterned with the resist mask RM
1
used as an etching mask. This serves as a hardmask.
Next, in the step of
FIG. 18
, the platinum film
12
is patterned with this hardmask used as an etching mask, to form the capacitor lower electrode. After that, the silicon oxide film
13
serving as the hardmask is removed with the silicon nitride film
11
in an underlying layer located below the capacitor used as an etching stopper.
Next, in the step of
FIG. 19
, a capacitor dielectric film
14
is so formed as to cover the platinum film
12
serving as the capacitor lower electrode and on the capacitor dielectric film
14
, a conductive film is formed as a capacitor upper electrode
15
. The capacitor lower electrode
12
, the capacitor dielectric film
14
and the capacitor upper electrode
15
constitute a capacitor CP.
Further, besides the above-discussed background-art method, Japanese Patent Application Laid Open Gazette No. 9-266200 discloses a manufacturing technique as below, which is intended to achieve an easy microfabrication of ferroelectrics or platinum electrode.
Specifically, on a device insulating film formed on a semiconductor substrate, a multilayer film consisting of a lower platinum film, a ferroelectric film and an upper platinum film is formed and on the multilayer film, a titanium film whose thickness is a tenth or less of that of the multilayer film is formed. After patterning the titanium film with a photoresist film, the multilayer film is etched with a mixed gas of oxygen and chlorine, whose oxygen concentration is 40%, with the patterned titanium film used as an etching mask. After that, the titanium film is removed by etching with a chlorine gas.
Furthermore, Japanese Patent Application Laid Open Gazette No. 2000-183303 discloses a manufacturing technique as below, which is intended to achieve a microfabrication of ruthenium electrode with excellent anisotropy.
Specifically, on a silicon oxide film, a multilayer film consisting of a silicon nitride film, a ruthenium film and a platinum film is formed and on the multilayer film, another silicon oxide film is formed. After patterning the higher silicon oxide film with a photoresist film, the platinum film and the ruthenium film are etched with the patterned silicon oxide film used as an etching mask. Finally, the silicon oxide film used as the etching mask is removed with the silicon nitride film formed below the ruthenium film as an etching stopper.
In these cases, there is a problem in the step of patterning the capacitor lower electrode formed of a platinum-group element. Though the chemical etching contributes to the etching of the platinum-group element as discussed earlier, the platinum-group element has an etching characteristic of large temperature dependency and due to the temperature distribution on a wafer or among a plurality of wafers processed simultaneously, an etching speed (etching rate) disadvantageously becomes nonuniform on the wafer surface or among the simultaneously-processed wafers.
FIG. 20
shows the temperature dependencies in etching rates of platinum (Pt), silicon nitride film (SiN) and silicon oxide film (SiO
2
) in patterning the capacitor lower electrode, for example, under the etching condition that a chlorine gas and an argon gas are used as etching gas with respective flows of 120 sccm and 30 sccm and the pressure in a reaction chamber is 20×0.1333 Pa (20 mTorr).
In
FIG. 20
, the horizontal axis indicates wafer temperature (°C) and the vertical axis indicates etching rate (nm/min). As is clear from this graph, the temperature dependency of platinum (Pt) is considerably large.
This means that the etching rate of a platinum film is greatly affected by the temperature distribution on a wafer or among a plurality of wafers.
It is assumed now that the preset temperature of the wafer is 370° C. and the platinum film
12
having a thickness of 20 nm formed on the silicon nitride film
11
is patterned in the above-discussed manufacturing process. There arises a temperature distribution where the lowest temperature region has a temperature of 360° C. and the highest temperature region has a temperature of 380° C. on the main surface of the silicon substrate
1
, and there is a temperature difference of 20° C. on the main surface of the silicon substrate
1
.
If
Nguyen Thanh
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Renesas Technology Corp.
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