Semiconductor integration circuit device

Details Semiconductor integration circuit device Semiconductor integration circuit device

2002-01-08

2004-04-06

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S185200, C365S194000, C365S233100

Reexamination Certificate

active

06717877

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and more particularly to a technique effective to be utilized in a large scale integrated circuit including a memory circuit capable of performing high-speed reading operation.
JP-A-9-259589 discloses a technique for controlling a timing of an activation signal of a sense amplifier for amplifying data read out from a memory cell by means of a signal formed by using a signal on a dummy bit line.
SUMMARY OF THE INVENTION
Even when the signal on the dummy bit line is used to control the activation signal of the sense amplifier, it is necessary to set an input offset caused by scattering in a process of a pair element of the sense amplifier or a time margin corresponding to a worst case of scattering in a process in the timing control system. That is, in order to operate the sense amplifier exactly, it is necessary to set so that the activation time of the sense amplifier is delayed in accordance with the time margin required until a signal amount taking the offset into consideration is obtained or a time margin corresponding scattering in timing in a control circuit.
It is an object of the present invention to provide a semiconductor integrated circuit device including a memory circuit attaining high-speed operation corresponding to the capability of individual circuits. The above and other objects and novel features of the present invention will be apparent from the following description and the accompanying drawings of the specification.
Representatives of the inventions disclosed in the present application are summarized as follows: The timing signal for activating a sense amplifier which is supplied with a signal read out from a memory array and amplifies the signal can be delayed by a first variable delay circuit so that a timing difference of a dummy signal read out from a dummy memory cell and the timing signal of the sense amplifier can be detected by a detection circuit and be made small in accordance with an output of the detection circuit, and a relative timing difference of the dummy signal and the timing signal of the sense amplifier can be adjusted by a second variable delay circuit.


REFERENCES:
patent: 5841719 (1998-11-01), Hirata
patent: 6009040 (1999-12-01), Choi et al.
patent: 6225843 (2001-05-01), Taniguchi et al.
patent: 6229363 (2001-05-01), Eto et al.
patent: 6522567 (2003-02-01), Iwanari
patent: 9-259589 (1997-10-01), None

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