Electronic digital logic circuitry – With test facilitating feature
Patent
1997-03-28
2000-09-12
Tokar, Michael
Electronic digital logic circuitry
With test facilitating feature
326 39, H03K 1900
Patent
active
061182966
ABSTRACT:
In a semiconductor logic integrated circuit, scan-path-testable flipflop circuits are provided, and scan-path flipflop circuits having a through mode are provided at an input and an output of a macrocell. The scan-path-testable flipflop circuits and the scan-path flipflop circuits having the through mode are cascade-connected. At the time of preparing a test pattern for the scan path test, the test pattern is prepared on the assumption that the macrocell does not exist. On the other hand, a test pattern for testing the macrocell is prepared, and then, is substituted for corresponding flipflop circuit values in the scan pattern. If the scan path test is performed by using the test pattern thus prepared, the test for the macrocell can be executed simultaneously.
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VLSI Design, Oct. 1983, "Integrating the Approaches to Structured Design for Testability", Keith Gutfreund, pp. 34-43.
NEC Corporation
Tokar Michael
Tran Anh
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