Semiconductor integrated circuits with power reduction...

Details Semiconductor integrated circuits with power reduction... Semiconductor integrated circuits with power reduction...

2000-05-19

2001-07-31

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

C326S098000, C326S021000, C365S226000

Reexamination Certificate

active

06268741

ABSTRACT:

FURTHER CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation of application Ser. No. 09/141,563, filed on Aug. 28, 1998, now U.S. Pat. No. 6,154,062 which is a continuation of application Ser. No. 8/797,051, filed on Feb. 10, 1997 now U.S. Pat. No. 5,825,198; which is a continuation of application Ser. No. 8/620,686 filed on Mar. 21, 1996 (U.S. Pat. No. 5,606,265); which is a continuation of application Ser. No. 8/374,990 filed on Jan. 19, 1995 (U.S. Pat. No. 5,521,527); which is a continuation of application Ser. No. 8/178,020 filed on Jan. 6, 1994 (U.S. Pat. No. 5,408,144), the entire disclosures of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION AND SUMMARY OF THE INVENTION
The present invention relates to semiconductor integrated circuits suitable for high-speed and low-power operation, and particularly to a semiconductor integrated circuit formed of small-geometry MOS transistors.
The semiconductor integrated circuits have so far been developed toward the scaling down of MOS transistors. However, since the minute structure of MOS transistors reduces their breakdown voltage the more as the degree of the minuteness becomes greater, the operating voltage of the small-geometry MOS transistors must be lowered, as described in International Symposium on VLSI Technology, Systems and Applications, Proceedings of Technical Papers, pp.188-192(May 1989). The operating voltages of the semiconductors used in the battery-operated portable electronic apparatus must be further reduced for their low power consumption.
In order to maintain their high-speed operation under reduced operating voltages, it is also necessary to decrease the threshold voltage (V
T
) of the MOS transistors. The reason for this is that the operating speed is governed by the effective gate voltage of the MOS transistors, or the remainder of the subtraction of V
T
from the operating voltage, or that it increased with the increase of this effective gate voltage. For example, in a 16-gigabit DRAM which is expected to have 0.15 &mgr;m or below in effective channel length, about 4 nm in gate oxide film thickness, 1 V in standard operating voltage within chip and about 1.75 V in boosted word line voltage, the constant current threshold voltage of transistors is calculated to be −0.04 V. The term, constant current threshold voltage of transistors is the gate-source voltage under the conditions of a ratio, 30 of effective channel width to effective channel length and a drain current of 10 nA. In this case, the substrate-source voltage is 0, the junction temperature is 25° and a typical condition is assumed. For simplicity, the threshold voltage of p-channel MOS transistors is shown with the opposite sign.
When V
T
is reduced, however, the drain current cannot be completely cut off due to the drain current characteristic of the subthreshold region of MOS transistors. This problem will be described with reference to
FIG. 22A
which shows a conventional CMOS inverter. When the input signal IN to the CMOS inverter has a low level (=V
ss
), the n-channel MOS transistor M
N
is turned off. When the input signal IN has a high level (=V
ss
), the p-channel MOS transistor M
P
is turned off. Therefore, in either case, from the ideal point of view, no current flows from the high source voltage V
cc
through the CMOS inverter to the low source voltage V
ss
, or ground potential.
When the threshold voltage V
T
of the MOS transistors is reduced, however, the subthreshold characteristic cannot be neglected. As shown in
FIG. 22B
, the drain current I
DS
in the subthreshold region is proportional to the exponential function of the gate-source voltage V
GS
, and expressed by the following equation (1).
I
DS
=
I
0
·
W
W
0
·
10
V
GS
-
V
T
S
(
1
)
where W is the channel width of the MOS transistors, I
0
and W
0
are the current value and channel width used when V
T
is defined, and S is the subthreshold swing (the reciprocal of the gradient of the V
GS
−log I
DS
characteristic). Thus, the drain current in the subthreshold region (or the subthreshold current) flows even under V
GS
=0. The subthreshold current can be expressed by the following equation (2).
I
L
=
I
0
·
W
W
0
·
10
-
V
T
S
(
2
)
When the input signal to the CMOS inverter shown in
FIG. 22A
is not changed, or when it is not operated, the off-state transistor of the CMOS inverter is at V
GS
=0. Therefore, the current flowing from the high source voltage V
cc
through the CMOS inverter to the low source voltage V
ss
, or ground potential is the current I
L
which flows in the off-state transistor of the CMOS inverter.
This subthreshold current, as shown in
FIG. 22B
, is exponentially increased from I
L
to I
L
′ when the threshold voltage is decreased from V
T
to V
T
′.
Although the increase of V
T
or the reduction of S reduce the subthreshold current as will be seen from the equation (2), the increase of V
T
, incurs the reduction of the speed due to the decrease of the effective gate voltage, while the reduction of S will be difficult for the following reason.
The subthreshold swing S can be expressed by using the capacitance C
OX
of the gate dielectric and the capacitance C
D
Of the depletion region under the gate as in the following equation (3).
S
=
k
·
T
·
l
n
⁢
10
q
⁢
1
+
C
D
C
OX
(
3
)
where k is the Boltzmann constant, T is the absolute temperature and q is the elementary charge. As will be seen from the equation (3), the condition of S≧kT l
n
10/q is limited for any values of C
OX
and C
D
. Thus, it is difficult for S to be reduced to 60 mV or below at room temperature (about 300 k).
Thus, in the semiconductor integrated circuit including MOS transistors with a low value of V
T
the amount of DC current consumption of non-operating circuits is remarkably increased because of the phenomenon mentioned above when the operating voltage becomes low (for example, 2 V or 2.5 V). Particularly, upon high-temperature operation, S becomes large, making this problem further serious. In the downsizing age of future computers and so on, when reduction of power is important, the increase of the subthreshold current becomes a substantial problem.
This problem will be further considered taking a memory, which is a typical semiconductor integrated circuit, as an example. The memory generally includes, as shown in
FIG. 23
, a memory array MA, an X decoder (XDEC) and word driver (WD) for selecting and driving a row line (word line W) for the selection of a memory cell MC within the memory array MA, a sense amplifier (SA) for amplifying the signal on a column line (data line D), a sense amplifier driving circuit (SAD) for driving the sense amplifier, a Y decoder (YDEC) for selecting a column line, and a peripheral circuit (PR) for controlling these circuits. The main parts of these circuits are designed based on the CMOS inverter logic circuit mentioned above.
When the threshold voltage V
T
of transistors (hereinafter, for simplicity the absolute values of the threshold voltages of the p-channel and n-channel MOS transistors are assumed to be equal to V
T
) is low, a subthreshold current, that is a current flowing in the source-drain path of the MOS transistors of which the V
GS
, is substantially 0.
Therefore, the sum of the subthreshold currents becomes particularly great in the circuits having a large number of MOS transistors, such as decoders, drivers or the peripheral circuit section.
For example, in the decoders or drivers, a small number of particular circuits are selected from a large number of circuits of the same type by the address signal, and driven.
FIG. 24
shows an example of the conventional word driver for DRAM.
If the threshold value V
T
of the MOS transistors of all CMOS drivers #1-#r is large enough, the subthreshold current, that is a current flowing in the source-drain paths of the MOS transistors of substantially zero V
GS
, is substantially zero in each of a large number of

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