Semiconductor integrated circuitry and method for...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C438S197000

Reexamination Certificate

active

07081649

ABSTRACT:
A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes7are formed via a gate insulating film6on the main surface of a semiconductor substrate1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer14composed of silicon nitride and a second side wall spacer15composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes19and21in a self-matching manner with respect to the first side wall spacers14and connecting portion is formed connecting a conductor20to a bit line BL. In addition, in the N channel MISFETs Qn1and Qn2, and in the P channel MISFET Qp1in areas other than the DRAM memory cell area, high density N-type semiconductor areas16and16bare formed, as well as a high density P-type semiconductor area17is formed in a self-matching manner with respect to the second side wall spacers15.

REFERENCES:
patent: 5364804 (1994-11-01), Ho et al.
patent: 5389558 (1995-02-01), Suwanai et al.
patent: 6037207 (2000-03-01), Asano et al.
patent: 6169324 (2001-01-01), Sugiura et al.
patent: 6503794 (2003-01-01), Watanabe et al.
patent: 3-276729 (1991-12-01), None
patent: 8-139314 (1996-05-01), None

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