Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2007-05-15
2007-05-15
Chung, Phung My (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S801000, C714S746000, C365S201000
Reexamination Certificate
active
10170583
ABSTRACT:
A semiconductor integrated circuit with memory redundancy circuit to address the problems of increased area, power consumption and access time which is caused by using an ECC circuit for error correction. The circuit comprises: a plurality of memory mats; a local bus, parallel to word lines, which transfers read data and write data from memory cells; a global bus for writing, parallel to data lines, which transfers write data from an input pad IO; a global bus for reading, parallel to data lines, which transfers read data to an output pad IO; and at least one error correction circuit located at an intersection of the global buses and the local bus. Reading and writing may each be completed in a single cycle, and during a write operation, data which is different from data previously read is written. By this configuration, an increase in area and power consumption can be avoided and errors such as soft errors can be corrected.
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patent: 5546410 (1996-08-01), Ando et al.
patent: 6065146 (2000-05-01), Bosshart
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Harada Masashige
Ishibashi Koichiro
Kijima Takehiko
Osada Kenichi
Saitou Yoshikazu
A. Marquez, Esq. Juan Carlos
Chung Phung My
Fisher Esq. Stanley P.
Hitachi ULSI Systems Co. Ltd.
Reed Smith LLP
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