Semiconductor integrated circuit with memory redundancy circuit

Details Semiconductor integrated circuit with memory redundancy circuit Semiconductor integrated circuit with memory redundancy circuit

2007-05-15

2007-05-15

Chung, Phung My (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S801000, C714S746000, C365S201000

Reexamination Certificate

active

10170583

ABSTRACT:
A semiconductor integrated circuit with memory redundancy circuit to address the problems of increased area, power consumption and access time which is caused by using an ECC circuit for error correction. The circuit comprises: a plurality of memory mats; a local bus, parallel to word lines, which transfers read data and write data from memory cells; a global bus for writing, parallel to data lines, which transfers write data from an input pad IO; a global bus for reading, parallel to data lines, which transfers read data to an output pad IO; and at least one error correction circuit located at an intersection of the global buses and the local bus. Reading and writing may each be completed in a single cycle, and during a write operation, data which is different from data previously read is written. By this configuration, an increase in area and power consumption can be avoided and errors such as soft errors can be corrected.

REFERENCES:
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patent: 5546410 (1996-08-01), Ando et al.
patent: 6065146 (2000-05-01), Bosshart
patent: 6665209 (2003-12-01), Osada et al.
patent: 61-50295 (1984-08-01), None
patent: 11-212877 (1998-01-01), None

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