Semiconductor integrated circuit with delay test circuit,...

Details Semiconductor integrated circuit with delay test circuit,... Semiconductor integrated circuit with delay test circuit,...

2006-02-07

2009-11-03

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S025000, C714S030000, C714S724000, C714S726000, C714S727000, C714S729000, C714S741000

Reexamination Certificate

active

07613971

ABSTRACT:
A semiconductor integrated circuit includes an input side flip-flop; a combinational circuit having an input connected with the input side flip-flop; an output side flip-flop connected with an output of the combinational circuit; and a delay test circuit. The delay test circuit generates output clock pulses by removing an optional one from equal to or more than 3 continuing clock pulses of an input clock signal, and supplies the output clock pulse to the input side flip-flop and the output side flip-flop.

REFERENCES:
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patent: 7194669 (2007-03-01), Nadeau-Dostie
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patent: 2004/0153926 (2004-08-01), Abdel-Hafez et al.
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patent: 2005/0262409 (2005-11-01), Wang et al.
patent: 2006/0064616 (2006-03-01), Rajski et al.
patent: 2007/0283201 (2007-12-01), Grise et al.
patent: 2002-196046 (2002-07-01), None
Sato, Y., et al., “DFT Timing Design Methodology for At-Speed BIST”, Proceedings of the ASP-DAC 2003, pp. 763-768 (Jan. 21-24, 2003).

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