Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
1999-03-18
2002-04-23
Heckler, Thomas M. (Department: 2182)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C714S042000
Reexamination Certificate
active
06378078
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a supervisory circuit for supervising an illicit address operation on a semiconductor integrated circuit and, more particularly, to an illicit address operation supervisory circuit for a microcomputer having an address bus line for memory addressing.
Conventionally, a microcomputer integrated on a semiconductor substrate designates (addressing) by a program counter a location on a ROM (Read Only Memory) where a program to be executed is stored, and reads out data from the ROM.
In the conventional microcomputer, the program counter outputs an address designating a location on the ROM to an address bus line between the program counter and ROM. If, therefore, a signal is supplied to the address bus between the program counter and ROM by bringing a probe or the like into contact with the address bus, the address flowing through the address bus line can be illicitly rewritten. The conventional microcomputer does not have any means for detecting such illicit address operation.
The conventional microcomputer suffers a security problem of undesirably allowing an illicit address operation for access to the ROM so as to execute a specific program stored in the ROM or read out data from the ROM.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a supervisory circuit for a semiconductor integrated circuit capable of realizing security with respect to an illicit address operation.
To achieve the above object, according to the present invention, there is provided a supervisory circuit for a semiconductor integrated circuit, comprising a first circuit for outputting an address signal, a second circuit for receiving via an address bus the address signal transferred from the first circuit, holding means for holding at least an address signal preceding one transfer period as a past address signal on the address bus, and first comparison means for comparing the past address signal held by the holding means with a current address signal on the address bus, and when a comparison result represents that the past and current address signals are identical, outputting an illicit operation detection signal.
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Heckler Thomas M.
NEC Corporation
Sughrue & Mion, PLLC
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