Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1982-05-24
1985-02-05
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
365221, G11C 700
Patent
active
044981554
ABSTRACT:
A semiconductor memory device of the single-chip MOS/LSI integrated circuit type has both serial access and random access means on the same chip. When the device is addressed for random access then data input or output is the same as in dynamic RAM operation, but if the address is for serial operation then access is different. For a serial read operation a row containing the addressed data is transferred to a shift register coupled to the random access array, and the shift register is clocked out. For serial write, data is clocked into the shift register then this row of data is transferred into the columns of the array.
REFERENCES:
patent: 3685020 (1972-08-01), Meade
patent: 4044339 (1977-08-01), Berg
patent: 4106109 (1978-08-01), Fassbender
patent: 4198697 (1980-04-01), Kuo et al.
patent: 4347587 (1982-08-01), Rao
Proceedings of the National Electronics Conference, Oct. 1, 1975, vol. 30, pp. 257-260, "Silicon: The Future Mass Memory"; R. C. Foss.
Graham John G.
Popek Joseph A.
Texas Instruments Incorporated
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