Electronic digital logic circuitry – With test facilitating feature
Reexamination Certificate
2000-12-13
2002-02-12
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
With test facilitating feature
C714S724000, C714S728000
Reexamination Certificate
active
06346822
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a diagnosis function for diagnosing a circuit operation.
2. Description of the Related Art
In order to reduce the number of inferior products of available semiconductor integrated circuits, at the stage of initial inspection, it is necessary to remove the semiconductor integrated circuits which have possibility of failure owing to infant mortality. For this purpose, the operation of a semiconductor integrated circuit is verified by externally monitoring an output signal in response to an input signal supplied to the semiconductor integrated circuit.
In recent years, the semiconductor integrated circuit has been subjected to “burn-in” testing in which stress is applied to the semiconductor integrated circuit in a state where it is set within a constant temperature chamber and the semiconductor integrated circuit is tested acceleratively.
Where the operation of the semiconductor integrated circuit is tested, it is preferable to monitor the signals produced from all the terminals of the semiconductor integrated circuit. However, generally, since a plurality of semiconductor integrated circuits are tested simultaneously, it is almost impossible to monitor the signals from all the terminals of each of the semiconductor integrated circuits.
Further, in the burn-in testing, the number of connecting wires, which can be connected to the semiconductor integrated circuit located in the chamber, is limited. Therefore, it is desired to test the semiconductor integrated circuit using a necessary minimum number of connecting wires.
SUMMARY OF THE INVENTION
The present invention has been accomplished under the above circumstance.
An object of the invention is to provide a semiconductor integrated circuit which has a diagnosis function capable of diagnosing its operation state using a necessary minimum number of connecting wires connectable to itself.
In order to attain the above object, in accordance with the first aspect of the invention, there is provided a semiconductor integrated circuit having a diagnosis function comprising: a logic circuit to which a random number pattern is supplied, said logic circuit designed in a scan-path manner and having a plurality of flip-flops which can be shift-registered; a first shift register for storing required bits of a first random number pattern shifted by said logic circuit; a second shift register for storing required bits of a first random number pattern supplied to said logic circuit; and means for comparing corresponding bits of the random number patterns stored in the first and the second shift register to detect whether all the bits of the first and second random number patterns agree or disagree with each other, thereby verifying a normal operation of said logic circuit.
In this configuration, the operating state of the logic circuit can be verified by detecting whether corresponding bits of the random number patterns supplied to the logic circuit and passed therethrough agree (agreement of all bits) or agree in their inverted state (agreement of inverted all bits) with each other.
In accordance with the second aspect of the invention, there is a provided semiconductor integrated circuit having a diagnosis function comprising: a logic circuit to which a pseudorandom number pattern of a string of M bits touring at a period of (2
M
−1) and not having a repetition within the period is supplied, said logic circuit designed in a scan-path manner and having a plurality of flip-flops which can be shift-registered; a shift register for storing required bits of a first random number pattern shifted by said logic circuit; holding means for holding data for comparison composed of any string of bits of said pseudorandom number pattern; and comparing means for comparing corresponding bits of the random number pattern stored in said shift register and data for comparison held in said holding means to detect whether all the bits of the random number patterns agree and/or disagree with each other, thereby verifying a normal operation of said logic circuit.
In this configuration, noting that strings of bits of a pseudorandom number pattern touring at a prescribed period are not repeated within the period, data corresponding to any one of strings of bits constituting the pseudorandom number pattern is set for comparison. The operating state of the logic circuit can be verified by detecting whether corresponding bits of the set data for comparison and the pseudorandom number pattern passed through the logic circuit agree (agreement of all bits) and/or agree in their inverted state (agreement of inverted all bits) with each other.
In accordance with the first and the second aspect of the invention, the signal indicative of the normal operation of the logic circuit can be derived through a single connecting wire so that it is not necessary to connect connecting wires to all the terminals of the logic circuit. This permits the operating state of the semiconductor integrated circuit to be diagnosed using a necessary and minimum number of connecting wires. Further, in accordance with the second aspect of the invention, using a periodical random number pattern, the data to be compared with the data passed through the logic circuit is previously fixed. This makes it unnecessary to take in the data for comparison, thereby reducing the circuit scale.
Preferably, the semiconductor integrated circuit having a diagnosis function further includes determination means which produces a success decision signal when the normal operation of said logic circuit is verified by said comparing means and an error decision signal when the normal operation of said logic circuit is not verified within a prescribed time by said comparing means.
In this configuration, the operating state of the logic circuit can be verified in the above manner within the limited time.
Namely, since the operating state of the semiconductor integrated circuit can be diagnosed with a limited time, where the agreement/disagreement of all bits is not detected owing to failure of the operation within the limited time, diagnosis is stopped immediately to save the time required for diagnosis.
Preferably, the semiconductor integrated circuit having a diagnosis function further includes random number generating means for said random number pattern or pseudorandom number pattern, wherein the logic circuit is subjected to burn-in testing of applying suitable stress to said logic circuit, thereby verifying the normal operation of said logic circuit.
This configuration does not require the connecting wire for supplying the random number pat tern to the semiconductor integrated circuit.
Specifically, since the terminals of the semiconductor integrated circuit are not occupied to supply the random pattern or pseudorandom pattern, the semiconductor integrated circuit can be diagnosed using the necessary and minimum number of connecting wires inclusive of the input terminals. This is particularly efficient for executing the burn-in testing in which the number of connecting wires connectable to the semiconductor integrated circuit is limited.
The above and other objects and features of the invention will be more apparent from the following description taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 4503537 (1985-03-01), McAnney
patent: 4513418 (1985-04-01), Bardell, Jr. et al.
patent: 4519078 (1985-05-01), Komonytsky
patent: 4683569 (1987-07-01), Rubin
patent: 6061817 (2000-05-01), Jones et al.
patent: 6134652 (2000-10-01), Warren
Chang Daniel D.
Tokar Michael
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